frontend/ir/ir_emitter: Add A32 equivalent to A64's SetCheckBit

This will be used in a subsequent change to implement ARMv6T2's CBZ/CBNZ
Thumb-1 instructions.
This commit is contained in:
Lioncash
2019-05-03 18:28:02 -04:00
committed by MerryMage
parent 1c47e638fc
commit bd755ae494
7 changed files with 29 additions and 3 deletions

View File

@@ -106,6 +106,10 @@ void IREmitter::SetCpsrNZCVQ(const IR::U32& value) {
Inst(Opcode::A32SetCpsrNZCVQ, value);
}
void IREmitter::SetCheckBit(const IR::U1& value) {
Inst(Opcode::A32SetCheckBit, value);
}
IR::U1 IREmitter::GetCFlag() {
return Inst<IR::U1>(Opcode::A32GetCFlag);
}

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@@ -51,6 +51,7 @@ public:
void SetCpsr(const IR::U32& value);
void SetCpsrNZCV(const IR::U32& value);
void SetCpsrNZCVQ(const IR::U32& value);
void SetCheckBit(const IR::U1& value);
IR::U1 GetCFlag();
void SetNFlag(const IR::U1& value);
void SetZFlag(const IR::U1& value);

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@@ -477,10 +477,15 @@ bool Inst::IsCoprocessorInstruction() const {
}
}
bool Inst::IsSetCheckBitOperation() const {
return op == Opcode::A32SetCheckBit ||
op == Opcode::A64SetCheckBit;
}
bool Inst::MayHaveSideEffects() const {
return op == Opcode::PushRSB ||
op == Opcode::A64SetCheckBit ||
op == Opcode::A64DataCacheOperationRaised ||
IsSetCheckBitOperation() ||
IsBarrier() ||
CausesCPUException() ||
WritesToCoreRegister() ||

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@@ -99,6 +99,9 @@ public:
/// Determines whether or not this instruction causes a CPU exception.
bool CausesCPUException() const;
/// Determines whether or not this instruction is a SetCheckBit operation.
bool IsSetCheckBitOperation() const;
/// Determines whether or not this instruction may have side-effects.
bool MayHaveSideEffects() const;

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@@ -5,6 +5,7 @@ OPCODE(Identity, Opaque, Opaq
OPCODE(Breakpoint, Void, )
// A32 Context getters/setters
A32OPC(SetCheckBit, Void, U1 )
A32OPC(GetRegister, U32, A32Reg )
A32OPC(GetExtendedRegister32, U32, A32ExtReg )
A32OPC(GetExtendedRegister64, U64, A32ExtReg )