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A64: Implement LDNP/STNP

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LDNP and STNP indicate that a memory access is non-temporal/streaming
(i.e. unlikely to be repeated), allowing data caching to not be
performed. However, given this is only a hint, we can treat these two
instructions as regular LDP and STP instructions for the time being.
This commit is contained in:
Lioncash
2019-03-02 17:03:08 -05:00
committed by MerryMage
parent 20fabc5083
commit bfaeb08d3c
4 changed files with 28 additions and 8 deletions
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6
src/frontend/A64/translate/impl/impl.h
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@@ -256,10 +256,8 @@ struct TranslatorVisitor final {
bool PRFM_lit(Imm<19> imm19, Imm<5> prfop);
// Loads and stores - Load/Store no-allocate pair
bool STNP_gen(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
bool LDNP_gen(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
bool STNP_fpsimd(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
bool LDNP_fpsimd(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
bool STNP_LDNP_gen(Imm<1> upper_opc, Imm<1> L, Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
bool STNP_LDNP_fpsimd(Imm<2> opc, Imm<1> L, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
// Loads and stores - Load/Store register pair
bool STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);