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IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64}

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This implementation just falls-back to the software floating point implementation.
This commit is contained in:
MerryMage
2018-06-30 10:49:47 +01:00
parent 760cc3ca89
commit caaf36dfd6
12 changed files with 159 additions and 173 deletions
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16
src/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
View File

@@ -38,13 +38,13 @@ bool TranslatorVisitor::FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
IR::U32U64 intval;
if (intsize == 32 && *fltsize == 32) {
intval = ir.FPSingleToS32(fltval, true, true);
intval = ir.FPSingleToFixedS32(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 32 && *fltsize == 64) {
intval = ir.FPDoubleToS32(fltval, true, true);
intval = ir.FPDoubleToFixedS32(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 64 && *fltsize == 32) {
return InterpretThisInstruction();
intval = ir.FPSingleToFixedS64(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 64 && *fltsize == 64) {
return InterpretThisInstruction();
intval = ir.FPDoubleToFixedS64(fltval, 0, FP::RoundingMode::TowardsZero);
} else {
UNREACHABLE();
}
@@ -69,13 +69,13 @@ bool TranslatorVisitor::FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
IR::U32U64 intval;
if (intsize == 32 && *fltsize == 32) {
intval = ir.FPSingleToU32(fltval, true, true);
intval = ir.FPSingleToFixedU32(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 32 && *fltsize == 64) {
intval = ir.FPDoubleToU32(fltval, true, true);
intval = ir.FPDoubleToFixedU32(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 64 && *fltsize == 32) {
return InterpretThisInstruction();
intval = ir.FPSingleToFixedU64(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 64 && *fltsize == 64) {
return InterpretThisInstruction();
intval = ir.FPDoubleToFixedU64(fltval, 0, FP::RoundingMode::TowardsZero);
} else {
UNREACHABLE();
}

16
src/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
View File

@@ -146,13 +146,13 @@ bool TranslatorVisitor::FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
IR::U32U64 intval;
if (intsize == 32 && *fltsize == 32) {
intval = ir.FPSingleToS32(fltval, true, true);
intval = ir.FPSingleToFixedS32(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 32 && *fltsize == 64) {
intval = ir.FPDoubleToS32(fltval, true, true);
intval = ir.FPDoubleToFixedS32(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 64 && *fltsize == 32) {
return InterpretThisInstruction();
intval = ir.FPSingleToFixedS64(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 64 && *fltsize == 64) {
return InterpretThisInstruction();
intval = ir.FPDoubleToFixedS64(fltval, 0, FP::RoundingMode::TowardsZero);
} else {
UNREACHABLE();
}
@@ -173,13 +173,13 @@ bool TranslatorVisitor::FCVTZU_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
IR::U32U64 intval;
if (intsize == 32 && *fltsize == 32) {
intval = ir.FPSingleToU32(fltval, true, true);
intval = ir.FPSingleToFixedU32(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 32 && *fltsize == 64) {
intval = ir.FPDoubleToU32(fltval, true, true);
intval = ir.FPDoubleToFixedU32(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 64 && *fltsize == 32) {
return InterpretThisInstruction();
intval = ir.FPSingleToFixedU64(fltval, 0, FP::RoundingMode::TowardsZero);
} else if (intsize == 64 && *fltsize == 64) {
return InterpretThisInstruction();
intval = ir.FPDoubleToFixedU64(fltval, 0, FP::RoundingMode::TowardsZero);
} else {
UNREACHABLE();
}