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Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2

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This commit is contained in:
MerryMage
2016-07-08 17:09:18 +08:00
parent e93fb0ba2b
commit d0b48bfb59
9 changed files with 144 additions and 6 deletions
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6
src/frontend/decoder/thumb1.h
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@@ -56,7 +56,7 @@ private:
};
template <typename V>
static const std::array<Thumb1Matcher<V>, 7> g_thumb1_instruction_table {{
static const std::array<Thumb1Matcher<V>, 9> g_thumb1_instruction_table {{
#define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
@@ -64,7 +64,7 @@ static const std::array<Thumb1Matcher<V>, 7> g_thumb1_instruction_table {{
{ INST(&V::thumb1_LSL_imm, "LSL (imm)", "00000vvvvvmmmddd") },
{ INST(&V::thumb1_LSR_imm, "LSR (imm)", "00001vvvvvmmmddd") },
{ INST(&V::thumb1_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd") },
//{ INST(&V::thumb1_ADD_rrr, "ADD (rrr)", "0001100mmmnnnddd") },
{ INST(&V::thumb1_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd") },
//{ INST(&V::thumb1_SUB_rrr, "SUB (rrr)", "0001101mmmnnnddd") },
//{ INST(&V::thumb1_ADD_rri, "ADD (rri)", "0001110mmmnnnddd") },
//{ INST(&V::thumb1_SUB_rri, "SUB (rri)", "0001111mmmnnnddd") },
@@ -92,7 +92,7 @@ static const std::array<Thumb1Matcher<V>, 7> g_thumb1_instruction_table {{
//{ INST(&V::thumb1_MVNS_rr, "MVNS (rr)", "0100001111mmmddd") },
// Special data instructions
//{ INST(&V::thumb1_ADD_high, "ADD (high)", "01000100dmmmmddd") }, // v4T, Low regs: v6T2
{ INST(&V::thumb1_ADD_reg_t2, "ADD (reg, T2)", "01000100Dmmmmddd") }, // v4T, Low regs: v6T2
//{ INST(&V::thumb1_CMP_high, "CMP (high)", "01000101dmmmmddd") }, // v4T
//{ INST(&V::thumb1_MOV_high, "MOV (high)", "01000110dmmmmddd") }, // v4T, Low regs: v6

9
src/frontend/disassembler_thumb.cpp
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@@ -114,6 +114,10 @@ public:
return Common::StringFromFormat("asrs %s, %s, #%u", RegStr(d), RegStr(m), imm5);
}
std::string thumb1_ADD_reg_t1(Reg m, Reg n, Reg d) {
return Common::StringFromFormat("adds %s, %s, %s", RegStr(d), RegStr(n), RegStr(m));
}
std::string thumb1_LSL_reg(Reg d_n, Reg m) {
return Common::StringFromFormat("lsls %s, %s", RegStr(d_n), RegStr(m));
}
@@ -126,6 +130,11 @@ public:
return Common::StringFromFormat("asrs %s, %s", RegStr(d_n), RegStr(m));
}
std::string thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
return Common::StringFromFormat("add %s, %s", RegStr(d_n), RegStr(m));
}
std::string thumb1_UDF() {
return Common::StringFromFormat("udf");
}

9
src/frontend/ir/ir.h
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@@ -100,6 +100,15 @@ private:
intptr_t tag;
};
/// Representation of a u1 immediate.
class ImmU1 final : public Value {
public:
explicit ImmU1(bool value_) : Value(Opcode::ImmU1), value(value_) {}
~ImmU1() override = default;
const bool value; ///< Literal value to load
};
/// Representation of a u8 immediate.
class ImmU8 final : public Value {
public:

2
src/frontend/ir/opcodes.inc
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@@ -20,6 +20,7 @@ OPCODE(SetVFlag, T::Void, T::U1
// Pseudo-operation, handled specially at final emit
OPCODE(GetCarryFromOp, T::U1, T::U32 )
OPCODE(GetOverflowFromOp, T::U1, T::U32 )
// Calculations
OPCODE(LeastSignificantByte, T::U8, T::U32 )
@@ -28,3 +29,4 @@ OPCODE(IsZero, T::U1, T::U32
OPCODE(LogicalShiftLeft, T::U32, T::U32, T::U8, T::U1 )
OPCODE(LogicalShiftRight, T::U32, T::U32, T::U8, T::U1 )
OPCODE(ArithmeticShiftRight, T::U32, T::U32, T::U8, T::U1 )
OPCODE(AddWithCarry, T::U32, T::U32, T::U32, T::U1 )

34
src/frontend/ir_emitter.cpp
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@@ -14,13 +14,29 @@ void IREmitter::Unimplemented() {
}
IR::ValuePtr IREmitter::Imm1(bool value) {
auto imm1 = std::make_shared<IR::ImmU1>(value);
AddToBlock(imm1);
return imm1;
}
IR::ValuePtr IREmitter::Imm8(u8 i) {
auto imm8 = std::make_shared<IR::ImmU8>(i);
AddToBlock(imm8);
return imm8;
}
IR::ValuePtr IREmitter::GetRegister(Dynarmic::Arm::Reg reg) {
IR::ValuePtr IREmitter::Imm32(u32 i) {
auto imm32 = std::make_shared<IR::ImmU32>(i);
AddToBlock(imm32);
return imm32;
}
IR::ValuePtr IREmitter::GetRegister(Reg reg) {
if (reg == Reg::PC) {
u32 offset = current_location.TFlag ? 4 : 8;
return Imm32(current_location.arm_pc + offset);
}
return Inst(IR::Opcode::GetRegister, { RegRef(reg) });
}
@@ -28,6 +44,11 @@ void IREmitter::SetRegister(const Reg reg, IR::ValuePtr value) {
Inst(IR::Opcode::SetRegister, { RegRef(reg), value });
}
void IREmitter::ALUWritePC(IR::ValuePtr value) {
// This behaviour is ARM version-dependent.
ASSERT_MSG(false, "Unimplemented");
}
IR::ValuePtr IREmitter::GetCFlag() {
return Inst(IR::Opcode::GetCFlag, {});
}
@@ -44,6 +65,10 @@ void IREmitter::SetCFlag(IR::ValuePtr value) {
Inst(IR::Opcode::SetCFlag, {value});
}
void IREmitter::SetVFlag(IR::ValuePtr value) {
Inst(IR::Opcode::SetVFlag, {value});
}
IR::ValuePtr IREmitter::LeastSignificantByte(IR::ValuePtr value) {
return Inst(IR::Opcode::LeastSignificantByte, {value});
}
@@ -74,6 +99,13 @@ IREmitter::ResultAndCarry IREmitter::ArithmeticShiftRight(IR::ValuePtr value_in,
return {result, carry_out};
}
IREmitter::ResultAndCarryAndOverflow IREmitter::AddWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in) {
auto result = Inst(IR::Opcode::AddWithCarry, {a, b, carry_in});
auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result});
auto overflow = Inst(IR::Opcode::GetOverflowFromOp, {result});
return {result, carry_out, overflow};
}
void IREmitter::SetTerm(const IR::Terminal& terminal) {
ASSERT_MSG(block.terminal.which() == 0, "Terminal has already been set.");
block.terminal = terminal;

12
src/frontend/ir_emitter.h
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@@ -25,17 +25,28 @@ public:
IR::ValuePtr carry;
};
struct ResultAndCarryAndOverflow {
IR::ValuePtr result;
IR::ValuePtr carry;
IR::ValuePtr overflow;
};
void Unimplemented();
IR::ValuePtr Imm1(bool value);
IR::ValuePtr Imm8(u8 value);
IR::ValuePtr Imm32(u32 value);
IR::ValuePtr GetRegister(Reg source_reg);
void SetRegister(const Reg dest_reg, IR::ValuePtr value);
void ALUWritePC(IR::ValuePtr value);
IR::ValuePtr GetCFlag();
void SetNFlag(IR::ValuePtr value);
void SetZFlag(IR::ValuePtr value);
void SetCFlag(IR::ValuePtr value);
void SetVFlag(IR::ValuePtr value);
IR::ValuePtr LeastSignificantByte(IR::ValuePtr value);
IR::ValuePtr MostSignificantBit(IR::ValuePtr value);
@@ -44,6 +55,7 @@ public:
ResultAndCarry LogicalShiftLeft(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
ResultAndCarry LogicalShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
ResultAndCarry ArithmeticShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
ResultAndCarryAndOverflow AddWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in);
void SetTerm(const IR::Terminal& terminal);

34
src/frontend/translate_thumb.cpp
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@@ -26,6 +26,10 @@ struct TranslatorVisitor final {
ir.SetTerm(IR::Term::Interpret(ir.current_location));
return false;
}
bool UnpredictableInstruction() {
ASSERT_MSG(false, "UNPREDICTABLE");
return false;
}
bool thumb1_LSL_imm(Imm5 imm5, Reg m, Reg d) {
u8 shift_n = imm5;
@@ -60,6 +64,17 @@ struct TranslatorVisitor final {
ir.SetCFlag(result.carry);
return true;
}
bool thumb1_ADD_reg_t1(Reg m, Reg n, Reg d) {
// ADDS <Rd>, <Rn>, <Rm>
// Note that it is not possible to encode Rd == R15.
auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
ir.SetRegister(d, result.result);
ir.SetNFlag(ir.MostSignificantBit(result.result));
ir.SetZFlag(ir.IsZero(result.result));
ir.SetCFlag(result.carry);
ir.SetVFlag(result.overflow);
return true;
}
bool thumb1_LSL_reg(Reg m, Reg d_n) {
const Reg d = d_n, n = d_n;
@@ -98,6 +113,25 @@ struct TranslatorVisitor final {
return true;
}
bool thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
Reg d = d_n, n = d_n;
if (n == Reg::PC && m == Reg::PC) {
return UnpredictableInstruction();
}
// ADD <Rdn>, <Rm>
auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
if (d == Reg::PC) {
ir.ALUWritePC(result.result);
// Return to dispatch as we can't predict what PC is going to be. Stop compilation.
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
} else {
ir.SetRegister(d, result.result);
return true;
}
}
bool thumb1_UDF() {
return TranslateThisInstruction();
}