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https://git.suyu.dev/suyu/dynarmic.git
synced 2026-03-06 02:26:30 +00:00
A64: Implement ADD_shifted
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@@ -70,29 +70,25 @@ U1 IREmitter::IsZero64(const U64& value) {
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}
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ResultAndCarry<U32> IREmitter::LogicalShiftLeft(const U32& value_in, const U8& shift_amount, const U1& carry_in) {
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auto result = Inst<U32>(Opcode::LogicalShiftLeft, value_in, shift_amount, carry_in);
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auto result = Inst<U32>(Opcode::LogicalShiftLeft32, value_in, shift_amount, carry_in);
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auto carry_out = Inst<U1>(Opcode::GetCarryFromOp, result);
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return {result, carry_out};
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}
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ResultAndCarry<U32> IREmitter::LogicalShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) {
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auto result = Inst<U32>(Opcode::LogicalShiftRight, value_in, shift_amount, carry_in);
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auto result = Inst<U32>(Opcode::LogicalShiftRight32, value_in, shift_amount, carry_in);
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auto carry_out = Inst<U1>(Opcode::GetCarryFromOp, result);
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return {result, carry_out};
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}
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U64 IREmitter::LogicalShiftRight64(const U64& value_in, const U8& shift_amount) {
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return Inst<U64>(Opcode::LogicalShiftRight64, value_in, shift_amount);
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}
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ResultAndCarry<U32> IREmitter::ArithmeticShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) {
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auto result = Inst<U32>(Opcode::ArithmeticShiftRight, value_in, shift_amount, carry_in);
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auto result = Inst<U32>(Opcode::ArithmeticShiftRight32, value_in, shift_amount, carry_in);
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auto carry_out = Inst<U1>(Opcode::GetCarryFromOp, result);
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return {result, carry_out};
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}
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ResultAndCarry<U32> IREmitter::RotateRight(const U32& value_in, const U8& shift_amount, const U1& carry_in) {
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auto result = Inst<U32>(Opcode::RotateRight, value_in, shift_amount, carry_in);
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auto result = Inst<U32>(Opcode::RotateRight32, value_in, shift_amount, carry_in);
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auto carry_out = Inst<U1>(Opcode::GetCarryFromOp, result);
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return {result, carry_out};
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}
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@@ -103,6 +99,42 @@ ResultAndCarry<U32> IREmitter::RotateRightExtended(const U32& value_in, const U1
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return {result, carry_out};
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}
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U64 IREmitter::LogicalShiftRight(const U64& value_in, const U8& shift_amount) {
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return Inst<U64>(Opcode::LogicalShiftRight64, value_in, shift_amount);
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}
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U32U64 IREmitter::LogicalShiftLeft(const U32U64& value_in, const U8& shift_amount) {
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if (value_in.GetType() == Type::U32) {
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return Inst<U32>(Opcode::LogicalShiftLeft32, value_in, shift_amount, Imm1(0));
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} else {
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return Inst<U64>(Opcode::LogicalShiftLeft64, value_in, shift_amount);
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}
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}
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U32U64 IREmitter::LogicalShiftRight(const U32U64& value_in, const U8& shift_amount) {
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if (value_in.GetType() == Type::U32) {
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return Inst<U32>(Opcode::LogicalShiftRight32, value_in, shift_amount, Imm1(0));
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} else {
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return Inst<U64>(Opcode::LogicalShiftRight64, value_in, shift_amount);
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}
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}
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U32U64 IREmitter::ArithmeticShiftRight(const U32U64& value_in, const U8& shift_amount) {
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if (value_in.GetType() == Type::U32) {
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return Inst<U32>(Opcode::ArithmeticShiftRight32, value_in, shift_amount, Imm1(0));
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} else {
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return Inst<U64>(Opcode::ArithmeticShiftRight64, value_in, shift_amount);
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}
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}
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U32U64 IREmitter::RotateRight(const U32U64& value_in, const U8& shift_amount) {
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if (value_in.GetType() == Type::U32) {
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return Inst<U32>(Opcode::RotateRight32, value_in, shift_amount, Imm1(0));
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} else {
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return Inst<U64>(Opcode::RotateRight64, value_in, shift_amount);
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}
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}
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ResultAndCarryAndOverflow<U32> IREmitter::AddWithCarry(const Value& a, const Value& b, const U1& carry_in) {
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auto result = Inst<U32>(Opcode::AddWithCarry, a, b, carry_in);
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auto carry_out = Inst<U1>(Opcode::GetCarryFromOp, result);
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@@ -114,10 +146,19 @@ U32 IREmitter::Add(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::AddWithCarry, a, b, Imm1(0));
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}
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U64 IREmitter::Add64(const U64& a, const U64& b) {
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U64 IREmitter::Add(const U64& a, const U64& b) {
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return Inst<U64>(Opcode::Add64, a, b);
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}
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U32U64 IREmitter::Add(const U32U64& a, const U32U64& b) {
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ASSERT(a.GetType() == b.GetType());
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if (a.GetType() == Type::U32) {
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return Inst<U32>(Opcode::AddWithCarry, a, b, Imm1(0));
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} else {
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return Inst<U64>(Opcode::Add64, a, b);
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}
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}
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ResultAndCarryAndOverflow<U32> IREmitter::SubWithCarry(const U32& a, const U32& b, const U1& carry_in) {
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// This is equivalent to AddWithCarry(a, Not(b), carry_in).
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auto result = Inst<U32>(Opcode::SubWithCarry, a, b, carry_in);
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@@ -130,7 +171,7 @@ U32 IREmitter::Sub(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::SubWithCarry, a, b, Imm1(1));
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}
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U64 IREmitter::Sub64(const U64& a, const U64& b) {
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U64 IREmitter::Sub(const U64& a, const U64& b) {
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return Inst<U64>(Opcode::Sub64, a, b);
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}
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@@ -138,7 +179,7 @@ U32 IREmitter::Mul(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::Mul, a, b);
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}
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U64 IREmitter::Mul64(const U64& a, const U64& b) {
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U64 IREmitter::Mul(const U64& a, const U64& b) {
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return Inst<U64>(Opcode::Mul64, a, b);
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}
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