SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-06 10:32:58 +00:00
Code Issues Packages Projects Releases Wiki Activity

A32: Implement ASIMD VRSQRTS

Browse Source
This commit is contained in:
MerryMage
2020-06-20 14:45:29 +01:00
parent 8f506c80c3
commit d3dc50d718
8 changed files with 37 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/frontend/A32/decoder/asimd.inc
View File

@@ -47,7 +47,7 @@ INST(asimd_VMUL_float, "VMUL (floating-point)", "111100110D0znnnndddd110
INST(asimd_VMAX_float, "VMAX (floating-point)", "111100100D0znnnndddd1111NQM0mmmm") // ASIMD
INST(asimd_VMIN_float, "VMIN (floating-point)", "111100100D1znnnndddd1111NQM0mmmm") // ASIMD
INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd1111NQM1mmmm") // ASIMD
//INST(asimd_VRSQRTS, "VRSQRTS", "111100100-1C--------1111---1----") // ASIMD
INST(asimd_VRSQRTS, "VRSQRTS", "111100100D1znnnndddd1111NQM1mmmm") // ASIMD
// Two registers and a scalar
//INST(asimd_VMLA_scalar, "VMLA (scalar)", "1111001U1-BB--------0x0x-1-0----") // ASIMD

6
src/frontend/A32/translate/impl/asimd_three_same.cpp
View File

@@ -419,4 +419,10 @@ bool ArmTranslatorVisitor::asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, b
});
}
bool ArmTranslatorVisitor::asimd_VRSQRTS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) {
return ir.FPVectorRSqrtStepFused(32, reg_n, reg_m, false);
});
}
} // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_arm.h
View File

@@ -472,6 +472,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VRSQRTS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
// Two registers and a shift amount
bool asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);

8
src/frontend/ir/ir_emitter.cpp
View File

@@ -2491,14 +2491,14 @@ U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) {
UNREACHABLE();
}
U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b) {
U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) {
switch (esize) {
case 16:
return Inst<U128>(Opcode::FPVectorRSqrtStepFused16, a, b);
return Inst<U128>(Opcode::FPVectorRSqrtStepFused16, a, b, Imm1(fpcr_controlled));
case 32:
return Inst<U128>(Opcode::FPVectorRSqrtStepFused32, a, b);
return Inst<U128>(Opcode::FPVectorRSqrtStepFused32, a, b, Imm1(fpcr_controlled));
case 64:
return Inst<U128>(Opcode::FPVectorRSqrtStepFused64, a, b);
return Inst<U128>(Opcode::FPVectorRSqrtStepFused64, a, b, Imm1(fpcr_controlled));
}
UNREACHABLE();
}

2
src/frontend/ir/ir_emitter.h
View File

@@ -364,7 +364,7 @@ public:
U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorSqrt(size_t esize, const U128& a);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);

6
src/frontend/ir/opcodes.inc
View File

@@ -625,9 +625,9 @@ OPCODE(FPVectorRoundInt64, U128, U128
OPCODE(FPVectorRSqrtEstimate16, U128, U128 )
OPCODE(FPVectorRSqrtEstimate32, U128, U128 )
OPCODE(FPVectorRSqrtEstimate64, U128, U128 )
OPCODE(FPVectorRSqrtStepFused16, U128, U128, U128 )
OPCODE(FPVectorRSqrtStepFused32, U128, U128, U128 )
OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128 )
OPCODE(FPVectorRSqrtStepFused16, U128, U128, U128, U1 )
OPCODE(FPVectorRSqrtStepFused32, U128, U128, U128, U1 )
OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128, U1 )
OPCODE(FPVectorSqrt32, U128, U128 )
OPCODE(FPVectorSqrt64, U128, U128 )
OPCODE(FPVectorSub32, U128, U128, U128, U1 )