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TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB

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This commit is contained in:
MerryMage
2016-08-09 22:48:20 +01:00
parent d921390928
commit df39308e03
12 changed files with 446 additions and 98 deletions
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41
src/frontend/ir/ir_emitter.cpp
View File

@@ -362,6 +362,15 @@ IR::Value IREmitter::FPSub64(const IR::Value& a, const IR::Value& b, bool fpscr_
return Inst(IR::Opcode::FPSub64, {a, b});
}
void IREmitter::ClearExlcusive() {
Inst(IR::Opcode::ClearExclusive, {});
}
void IREmitter::SetExclusive(const IR::Value& vaddr, size_t byte_size) {
ASSERT(byte_size == 1 || byte_size == 2 || byte_size == 4 || byte_size == 8 || byte_size == 16);
Inst(IR::Opcode::SetExclusive, {vaddr, Imm8(u8(byte_size))});
}
IR::Value IREmitter::ReadMemory8(const IR::Value& vaddr) {
return Inst(IR::Opcode::ReadMemory8, {vaddr});
}
@@ -412,6 +421,38 @@ void IREmitter::WriteMemory64(const IR::Value& vaddr, const IR::Value& value) {
}
}
IR::Value IREmitter::ExclusiveWriteMemory8(const IR::Value& vaddr, const IR::Value& value) {
return Inst(IR::Opcode::ExclusiveWriteMemory8, {vaddr, value});
}
IR::Value IREmitter::ExclusiveWriteMemory16(const IR::Value& vaddr, const IR::Value& value) {
if (current_location.EFlag()) {
auto v = ByteReverseHalf(value);
return Inst(IR::Opcode::ExclusiveWriteMemory16, {vaddr, v});
} else {
return Inst(IR::Opcode::ExclusiveWriteMemory16, {vaddr, value});
}
}
IR::Value IREmitter::ExclusiveWriteMemory32(const IR::Value& vaddr, const IR::Value& value) {
if (current_location.EFlag()) {
auto v = ByteReverseWord(value);
return Inst(IR::Opcode::ExclusiveWriteMemory32, {vaddr, v});
} else {
return Inst(IR::Opcode::ExclusiveWriteMemory32, {vaddr, value});
}
}
IR::Value IREmitter::ExclusiveWriteMemory64(const IR::Value& vaddr, const IR::Value& value_lo, const IR::Value& value_hi) {
if (current_location.EFlag()) {
auto vlo = ByteReverseWord(value_lo);
auto vhi = ByteReverseWord(value_hi);
return Inst(IR::Opcode::ExclusiveWriteMemory64, {vaddr, vlo, vhi});
} else {
return Inst(IR::Opcode::ExclusiveWriteMemory64, {vaddr, value_lo, value_hi});
}
}
void IREmitter::Breakpoint() {
Inst(IR::Opcode::Breakpoint, {});
}

6
src/frontend/ir/ir_emitter.h
View File

@@ -113,6 +113,8 @@ public:
IR::Value FPSub32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled);
IR::Value FPSub64(const IR::Value& a, const IR::Value& b, bool fpscr_controlled);
void ClearExlcusive();
void SetExclusive(const IR::Value& vaddr, size_t byte_size);
IR::Value ReadMemory8(const IR::Value& vaddr);
IR::Value ReadMemory16(const IR::Value& vaddr);
IR::Value ReadMemory32(const IR::Value& vaddr);
@@ -121,6 +123,10 @@ public:
void WriteMemory16(const IR::Value& vaddr, const IR::Value& value);
void WriteMemory32(const IR::Value& vaddr, const IR::Value& value);
void WriteMemory64(const IR::Value& vaddr, const IR::Value& value);
IR::Value ExclusiveWriteMemory8(const IR::Value& vaddr, const IR::Value& value);
IR::Value ExclusiveWriteMemory16(const IR::Value& vaddr, const IR::Value& value);
IR::Value ExclusiveWriteMemory32(const IR::Value& vaddr, const IR::Value& value);
IR::Value ExclusiveWriteMemory64(const IR::Value& vaddr, const IR::Value& value_lo, const IR::Value& value_hi);
void Breakpoint();

6
src/frontend/ir/opcodes.inc
View File

@@ -82,6 +82,8 @@ OPCODE(FPSub32, T::F32, T::F32, T::F32
OPCODE(FPSub64, T::F64, T::F64, T::F64 )
// Memory access
OPCODE(ClearExclusive, T::Void, )
OPCODE(SetExclusive, T::Void, T::U32, T::U8 )
OPCODE(ReadMemory8, T::U8, T::U32 )
OPCODE(ReadMemory16, T::U16, T::U32 )
OPCODE(ReadMemory32, T::U32, T::U32 )
@@ -90,3 +92,7 @@ OPCODE(WriteMemory8, T::Void, T::U32, T::U8
OPCODE(WriteMemory16, T::Void, T::U32, T::U16 )
OPCODE(WriteMemory32, T::Void, T::U32, T::U32 )
OPCODE(WriteMemory64, T::Void, T::U32, T::U64 )
OPCODE(ExclusiveWriteMemory8, T::U32, T::U32, T::U8 )
OPCODE(ExclusiveWriteMemory16, T::U32, T::U32, T::U16 )
OPCODE(ExclusiveWriteMemory32, T::U32, T::U32, T::U32 )
OPCODE(ExclusiveWriteMemory64, T::U32, T::U32, T::U32, T::U32 )