SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-06 02:26:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)

Browse Source
This commit is contained in:
Fernando Sahmkow
2018-01-25 20:57:56 -04:00
committed by MerryMage
parent cf824fb2b2
commit e0c12ec2ad
6 changed files with 81 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/frontend/A64/decoder/a64.inc
View File

@@ -836,8 +836,8 @@ INST(AND_asimd, "AND (vector)", "0Q001
//INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd")
//INST(FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd")
//INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd")
//INST(ORR_asimd_reg, "ORR (vector, register)", "0Q001110101mmmmm000111nnnnnddddd")
//INST(ORN_asimd, "ORN (vector)", "0Q001110111mmmmm000111nnnnnddddd")
INST(ORR_asimd_reg, "ORR (vector, register)", "0Q001110101mmmmm000111nnnnnddddd")
INST(ORN_asimd, "ORN (vector)", "0Q001110111mmmmm000111nnnnnddddd")
//INST(UHADD, "UHADD", "0Q101110zz1mmmmm000001nnnnnddddd")
//INST(URHADD, "URHADD", "0Q101110zz1mmmmm000101nnnnnddddd")
//INST(UHSUB, "UHSUB", "0Q101110zz1mmmmm001001nnnnnddddd")
@@ -849,7 +849,7 @@ INST(AND_asimd, "AND (vector)", "0Q001
//INST(PMUL, "PMUL", "0Q101110zz1mmmmm100111nnnnnddddd")
//INST(UMAXP, "UMAXP", "0Q101110zz1mmmmm101001nnnnnddddd")
//INST(UMINP, "UMINP", "0Q101110zz1mmmmm101011nnnnnddddd")
//INST(EOR_asimd, "EOR (vector)", "0Q101110001mmmmm000111nnnnnddddd")
INST(EOR_asimd, "EOR (vector)", "0Q101110001mmmmm000111nnnnnddddd")
//INST(BSL, "BSL", "0Q101110011mmmmm000111nnnnnddddd")
//INST(BIT, "BIT", "0Q101110101mmmmm000111nnnnnddddd")
//INST(BIF, "BIF", "0Q101110111mmmmm000111nnnnnddddd")