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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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committed by
MerryMage
parent
cf824fb2b2
commit
e0c12ec2ad
@@ -74,5 +74,45 @@ bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
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return true;
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}
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bool TranslatorVisitor::ORR_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
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const size_t datasize = Q ? 128 : 64;
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auto operand1 = V(datasize, Vn);
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auto operand2 = V(datasize, Vm);
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auto result = ir.VectorOr(operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::ORN_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
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const size_t datasize = Q ? 128 : 64;
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auto operand1 = V(datasize, Vn);
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auto operand2 = V(datasize, Vm);
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// TODO: This does not zero the upper 64 bits when datasize == 64. This may break future optimization passes.
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auto result = ir.VectorOr(operand1, ir.VectorNot(operand2));
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::EOR_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
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const size_t datasize = Q ? 128 : 64;
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auto operand1 = V(datasize, Vn);
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auto operand2 = V(datasize, Vm);
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auto result = ir.VectorEor(operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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} // namespace A64
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} // namespace Dynarmic
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