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Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)

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This commit is contained in:
MerryMage
2016-07-18 21:04:39 +01:00
parent 2363759c62
commit e0d6e28b67
6 changed files with 217 additions and 142 deletions
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10
src/frontend/decoder/thumb16.h
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@@ -141,12 +141,12 @@ boost::optional<const Thumb16Matcher<V>&> DecodeThumb16(u16 instruction) {
INST(&V::thumb16_LDMIA, "LDMIA", "11001nnnxxxxxxxx"),
// Branch instructions
//INST(&V::thumb16_BX, "BX (reg)", "010001110mmmm000"), // v4T
//INST(&V::thumb16_BLX, "BLX (reg)", "010001111mmmm000"), // v5T
INST(&V::thumb16_BX, "BX", "010001110mmmm000"), // v4T
INST(&V::thumb16_BLX_reg, "BLX (reg)", "010001111mmmm000"), // v5T
INST(&V::thumb16_UDF, "UDF", "11011110--------"),
INST(&V::thumb16_SVC, "SVC", "11011111xxxxxxxx"),
//INST(&V::thumb16_B_cond, "B (cond)", "1101ccccxxxxxxxx"),
//INST(&V::thumb16_B_imm, "B (imm)", "11100xxxxxxxxxxx"),
INST(&V::thumb16_B_t1, "B (T1)", "1101ccccvvvvvvvv"),
INST(&V::thumb16_B_t2, "B (T2)", "11100vvvvvvvvvvv"),
//INST(&V::thumb16_BLX_suffix, "BLX (imm, suffix)", "11101xxxxxxxxxx0"),
//INST(&V::thumb16_BLX_prefix, "BL/BLX (imm, prefix)", "11110xxxxxxxxxxx"),
//INST(&V::thumb16_BL_suffix, "BL (imm, suffix)", "11111xxxxxxxxxxx"),
@@ -157,8 +157,6 @@ boost::optional<const Thumb16Matcher<V>&> DecodeThumb16(u16 instruction) {
const auto matches_instruction = [instruction](const auto& matcher){ return matcher.Matches(instruction); };
assert(std::count_if(table.begin(), table.end(), matches_instruction) <= 1);
auto iter = std::find_if(table.begin(), table.end(), matches_instruction);
return iter != table.end() ? boost::make_optional<const Thumb16Matcher<V>&>(*iter) : boost::none;
}

17
src/frontend/disassembler/disassembler_thumb.cpp
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@@ -380,6 +380,13 @@ public:
return Common::StringFromFormat("ldm %s%s, %s", RegStr(n), write_back ? "!" : "", RegListStr(reg_list).c_str());
}
std::string thumb16_BX(Reg m) {
return Common::StringFromFormat("bx %s", RegStr(m));
}
std::string thumb16_BLX_reg(Reg m) {
return Common::StringFromFormat("blx %s", RegStr(m));
}
std::string thumb16_UDF() {
return Common::StringFromFormat("udf");
@@ -388,6 +395,16 @@ public:
std::string thumb16_SVC(Imm8 imm8) {
return Common::StringFromFormat("svc #%u", imm8);
}
std::string thumb16_B_t1(Cond cond, Imm8 imm8) {
s32 imm32 = Common::SignExtend<9, s32>(imm8 << 1) + 4;
return Common::StringFromFormat("b%s %s#%u", CondStr(cond), SignStr(imm32), abs(imm32));
}
std::string thumb16_B_t2(Imm11 imm11) {
s32 imm32 = Common::SignExtend<12, s32>(imm11 << 1) + 4;
return Common::StringFromFormat("b %s#%u", SignStr(imm32), abs(imm32));
}
};
std::string DisassembleThumb16(u16 instruction) {

10
src/frontend/ir/ir_emitter.cpp
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@@ -57,6 +57,10 @@ void IREmitter::SetRegister(const Reg reg, IR::ValuePtr value) {
void IREmitter::ALUWritePC(IR::ValuePtr value) {
// This behaviour is ARM version-dependent.
// The below implementation is for ARMv6k
BranchWritePC(value);
}
void IREmitter::BranchWritePC(IR::ValuePtr value) {
if (!current_location.TFlag) {
auto new_pc = And(value, Imm32(0xFFFFFFFC));
Inst(IR::Opcode::SetRegister, { RegRef(Reg::PC), new_pc });
@@ -66,10 +70,14 @@ void IREmitter::ALUWritePC(IR::ValuePtr value) {
}
}
void IREmitter::BXWritePC(IR::ValuePtr value) {
Inst(IR::Opcode::BXWritePC, {value});
}
void IREmitter::LoadWritePC(IR::ValuePtr value) {
// This behaviour is ARM version-dependent.
// The below implementation is for ARMv6k
Inst(IR::Opcode::BXWritePC, {value});
BXWritePC(value);
}
void IREmitter::CallSupervisor(IR::ValuePtr value) {

2
src/frontend/ir/ir_emitter.h
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@@ -43,6 +43,8 @@ public:
void SetRegister(const Reg dest_reg, IR::ValuePtr value);
void ALUWritePC(IR::ValuePtr value);
void BranchWritePC(IR::ValuePtr value);
void BXWritePC(IR::ValuePtr value);
void LoadWritePC(IR::ValuePtr value);
void CallSupervisor(IR::ValuePtr value);

40
src/frontend/translate/translate_thumb.cpp
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@@ -740,10 +740,50 @@ struct ThumbTranslatorVisitor final {
return InterpretThisInstruction();
}
bool thumb16_BX(Reg m) {
// BX <Rm>
ir.BXWritePC(ir.GetRegister(m));
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
bool thumb16_BLX_reg(Reg m) {
// BLX <Rm>
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.arm_pc + 2) | 1));
ir.BXWritePC(ir.GetRegister(m));
// TODO(optimization): Possible push RSB location
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
bool thumb16_SVC(Imm8 imm8) {
u32 imm32 = imm8;
// SVC #<imm8>
ir.CallSupervisor(ir.Imm32(imm32));
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
bool thumb16_B_t1(Cond cond, Imm8 imm8) {
s32 imm32 = Common::SignExtend<9, s32>(imm8 << 1) + 4;
if (cond == Cond::AL) {
return thumb16_UDF();
}
// B<cond> <label>
auto then_location = ir.current_location;
then_location.arm_pc += imm32;
auto else_location = ir.current_location;
else_location.arm_pc += 2;
ir.SetTerm(IR::Term::If{cond, IR::Term::LinkBlock{then_location}, IR::Term::LinkBlock{else_location}});
return false;
}
bool thumb16_B_t2(Imm11 imm11) {
s32 imm32 = Common::SignExtend<12, s32>(imm11 << 1) + 4;
// B <label>
auto next_location = ir.current_location;
next_location.arm_pc += imm32;
ir.SetTerm(IR::Term::LinkBlock{next_location});
return false;
}
};