TranslateArm: Implement MRS, MSR (imm), MSR (reg)

2026-02-18 22:42:58 +00:00 · 2016-08-14 19:39:16 +01:00
parent 30f3d869cc
commit e164ede4dc
9 changed files with 95 additions and 10 deletions
--- a/src/ir_opt/get_set_elimination_pass.cpp
+++ b/src/ir_opt/get_set_elimination_pass.cpp
@@ -92,6 +92,14 @@ void GetSetElimination(IR::Block& block) {
                do_get(v_info, inst);
                break;
            }
+            case IR::Opcode::SetCpsr:
+            case IR::Opcode::GetCpsr: {
+                n_info = {};
+                z_info = {};
+                c_info = {};
+                v_info = {};
+                break;
+            }
            default:
                break;
        }