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A64: Implement SQSHL's vector register variant

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Lioncash
2018-09-15 20:30:29 -04:00
committed by MerryMage
parent b14eaaec46
commit e8b0f25dff
2 changed files with 17 additions and 1 deletions
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src/frontend/A64/decoder/a64.inc
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@@ -709,7 +709,7 @@ INST(SQSUB_2, "SQSUB", "0Q001
INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd")
INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd")
INST(SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd")
//INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd")
INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd")
INST(SRSHL_2, "SRSHL", "0Q001110zz1mmmmm010101nnnnnddddd")
//INST(SQRSHL_2, "SQRSHL", "0Q001110zz1mmmmm010111nnnnnddddd")
INST(SMAX, "SMAX", "0Q001110zz1mmmmm011001nnnnnddddd")