A64: PSTATE access and tests

src/backend_x64/a64_emit_x64.cpp

@@ -128,7 +128,8 @@ void A64EmitX64::EmitA64SetNZCV(A64EmitContext& ctx, IR::Inst* inst) {
     Xbyak::Reg32 to_store = ctx.reg_alloc.UseGpr(args[0]).cvt32();
     code->and_(to_store, 0b11000001'00000001);
     code->imul(to_store, to_store, 0b00010000'00100001);
-    code->and_(to_store, 0xFF000000);
+    code->shl(to_store, 16);
+    code->and_(to_store, 0xF0000000);
     code->mov(dword[r15 + offsetof(A64JitState, CPSR_nzcv)], to_store);
 }
 

src/backend_x64/a64_interface.cpp

@@ -125,6 +125,14 @@ public:
         jit_state.SetFpcr(value);
     }
 
+    u32 GetPstate() const {
+        return jit_state.GetPstate();
+    }
+
+    void SetPstate(u32 value) {
+        jit_state.SetPstate(value);
+    }
+
     bool IsExecuting() const {
         return is_executing;
     }
@@ -257,6 +265,14 @@ void Jit::SetFpcr(u32 value) {
     impl->SetFpcr(value);
 }
 
+u32 Jit::GetPstate() const {
+    return impl->GetPstate();
+}
+
+void Jit::SetPstate(u32 value) {
+    impl->SetPstate(value);
+}
+
 bool Jit::IsExecuting() const {
     return impl->IsExecuting();
 }

src/backend_x64/a64_jitstate.h

@@ -33,6 +33,12 @@ struct A64JitState {
 
     u32 CPSR_nzcv = 0;
     u32 FPSCR_nzcv = 0;
+    u32 GetPstate() const {
+        return CPSR_nzcv;
+    }
+    void SetPstate(u32 new_pstate) {
+        CPSR_nzcv = new_pstate & 0xF0000000;
+    }
 
     alignas(16) std::array<u64, 64> vec{}; // Extension registers.