SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-26 07:09:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

A32: Implement ASIMD VDUP (ARM core register)

Browse Source
This commit is contained in:
MerryMage
2020-06-20 15:58:29 +01:00
parent 15ee562dd0
commit e8c460c167
4 changed files with 45 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/frontend/A32/disassembler/disassembler_arm.cpp
View File

@@ -119,6 +119,16 @@ public:
return fmt::format("{}{}", dp_operation ? 'd' : 's', reg_num + 1);
}
static std::string VectorStr(bool Q, size_t base, bool bit) {
size_t reg_num;
if (Q) {
reg_num = (base >> 1) + (bit ? 8 : 0);
} else {
reg_num = base + (bit ? 16 : 0);
}
return fmt::format("{}{}", Q ? 'q' : 'd', reg_num);
}
static std::string CondOrTwo(Cond cond) {
return cond == Cond::NV ? "2" : CondToString(cond);
}
@@ -1337,6 +1347,11 @@ public:
return fmt::format("vmov{} {}, {}, {}", CondToString(cond), t, t2, FPRegStr(true, Vm, M));
}
std::string vfp_VDUP(Cond cond, Imm<1> B, bool Q, size_t Vd, Reg t, bool D, Imm<1> E) {
const size_t esize = 32u >> concatenate(B, E).ZeroExtend();
return fmt::format("vdup{}.{} {}, {}", CondToString(cond), esize, VectorStr(Q, Vd, D), t);
}
std::string vfp_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm){
return fmt::format("vmov{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M));
}