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IR: Implement A64OrQC

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This commit is contained in:
MerryMage
2018-07-24 19:04:40 +01:00
parent f0fecf2615
commit ecbf9dbae5
5 changed files with 22 additions and 0 deletions
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4
src/frontend/A64/ir_emitter.cpp
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@@ -33,6 +33,10 @@ void IREmitter::SetNZCV(const IR::NZCV& nzcv) {
Inst(Opcode::A64SetNZCV, nzcv);
}
void IREmitter::OrQC(const IR::U1& value) {
Inst(Opcode::A64OrQC, value);
}
void IREmitter::CallSupervisor(u32 imm) {
Inst(Opcode::A64CallSupervisor, Imm32(imm));
}

1
src/frontend/A64/ir_emitter.h
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@@ -38,6 +38,7 @@ public:
void SetCheckBit(const IR::U1& value);
IR::U1 GetCFlag();
void SetNZCV(const IR::NZCV& nzcv);
void OrQC(const IR::U1& value);
void CallSupervisor(u32 imm);
void ExceptionRaised(Exception exception);

1
src/frontend/ir/microinstruction.cpp
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@@ -341,6 +341,7 @@ bool Inst::ReadsFromFPSRCumulativeSaturationBit() const {
bool Inst::WritesToFPSRCumulativeSaturationBit() const {
switch (op) {
case Opcode::A64OrQC:
case Opcode::VectorSignedSaturatedNarrowToSigned16:
case Opcode::VectorSignedSaturatedNarrowToSigned32:
case Opcode::VectorSignedSaturatedNarrowToSigned64:

1
src/frontend/ir/opcodes.inc
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@@ -59,6 +59,7 @@ A64OPC(SetQ, T::Void, T::A64Vec,
A64OPC(SetSP, T::Void, T::U64 )
A64OPC(SetFPCR, T::Void, T::U32 )
A64OPC(SetFPSR, T::Void, T::U32 )
A64OPC(OrQC, T::Void, T::U1 )
A64OPC(SetPC, T::Void, T::U64 )
A64OPC(CallSupervisor, T::Void, T::U32 )
A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 )