SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-25 02:28:40 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix VShift terminology

Browse Source 
An arithmetic shift is by definition a signed shift, and a logical shift is by definition an unsigned shift.

- Rename VectorLogicalVShiftS* -> VectorArithmeticVShift*
- Rename VectorLogicalVShiftU* -> VectorLogicalVShift*
This commit is contained in:
MerryMage
2018-09-23 10:50:39 +01:00
parent b51dae790d
commit f0920c0ded
6 changed files with 170 additions and 170 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/frontend/A64/translate/impl/simd_three_same.cpp
View File

@@ -817,7 +817,7 @@ bool TranslatorVisitor::SSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorLogicalVShiftSigned(esize, operand1, operand2);
const IR::U128 result = ir.VectorArithmeticVShift(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
@@ -839,7 +839,7 @@ bool TranslatorVisitor::USHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorLogicalVShiftUnsigned(esize, operand1, operand2);
const IR::U128 result = ir.VectorLogicalVShift(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}