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A64: Implement SQADD and SQSUB, scalar variant

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MerryMage
2018-07-30 11:00:20 +01:00
parent 10e196480f
commit f2393488fe
3 changed files with 46 additions and 24 deletions
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4
src/frontend/A64/decoder/a64.inc
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@@ -444,8 +444,8 @@ INST(FMINP_pair_2, "FMINP (scalar)", "01111
//INST(SQDMULL_vec_2, "SQDMULL, SQDMULL2 (vector)", "0Q001110zz1mmmmm110100nnnnnddddd")
// Data Processing - FP and SIMD - SIMD Scalar three same
//INST(SQADD_1, "SQADD", "01011110zz1mmmmm000011nnnnnddddd")
//INST(SQSUB_1, "SQSUB", "01011110zz1mmmmm001011nnnnnddddd")
INST(SQADD_1, "SQADD", "01011110zz1mmmmm000011nnnnnddddd")
INST(SQSUB_1, "SQSUB", "01011110zz1mmmmm001011nnnnnddddd")
INST(CMGT_reg_1, "CMGT (register)", "01011110zz1mmmmm001101nnnnnddddd")
INST(CMGE_reg_1, "CMGE (register)", "01011110zz1mmmmm001111nnnnnddddd")
INST(SSHL_1, "SSHL", "01011110zz1mmmmm010001nnnnnddddd")