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A32: Implement ASIMD VQSUB instruction

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This commit is contained in:
MerryMage
2020-05-30 16:10:51 +01:00
parent 16ff880f8f
commit f3845cea9a
8 changed files with 157 additions and 184 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@@ -11,7 +11,7 @@ INST(asimd_VBSL, "VBSL", "111100110D01nnnndddd000
INST(asimd_VBIT, "VBIT", "111100110D10nnnndddd0001NQM1mmmm") // ASIMD
INST(asimd_VBIF, "VBIF", "111100110D11nnnndddd0001NQM1mmmm") // ASIMD
INST(asimd_VHSUB, "VHSUB", "1111001U0Dzznnnndddd0010NQM0mmmm") // ASIMD
//INST(asimd_VQSUB, "VQSUB", "1111001U0-CC--------0010---1----") // ASIMD
INST(asimd_VQSUB, "VQSUB", "1111001U0Dzznnnndddd0010NQM1mmmm") // ASIMD
//INST(asimd_VCGT_reg, "VCGT (register)", "1111001U0-CC--------0011---0----") // ASIMD
//INST(asimd_VCGE_reg, "VCGE (register)", "1111001U0-CC--------0011---1----") // ASIMD
//INST(asimd_VSHL_reg, "VSHL (register)", "1111001U0-CC--------0100---0----") // ASIMD

27
src/frontend/A32/translate/impl/asimd_three_same.cpp
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@@ -74,9 +74,8 @@ bool ArmTranslatorVisitor::asimd_VQADD(bool U, bool D, size_t sz, size_t Vn, siz
const IR::U128 reg_n = ir.GetVector(n);
const IR::U128 reg_m = ir.GetVector(m);
const auto result = U ? ir.VectorUnsignedSaturatedAdd(esize, reg_n, reg_m) : ir.VectorSignedSaturatedAdd(esize, reg_n, reg_m);
ir.OrQFlag(result.overflow);
ir.SetVector(d, result.result);
const IR::U128 result = U ? ir.VectorUnsignedSaturatedAdd(esize, reg_n, reg_m) : ir.VectorSignedSaturatedAdd(esize, reg_n, reg_m);
ir.SetVector(d, result);
return true;
}
@@ -173,4 +172,26 @@ bool ArmTranslatorVisitor::asimd_VHSUB(bool U, bool D, size_t sz, size_t Vn, siz
return true;
}
bool ArmTranslatorVisitor::asimd_VQSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
if (sz == 0b11) {
return UndefinedInstruction();
}
const size_t esize = 8 << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto n = ToVector(Q, Vn, N);
const IR::U128 reg_n = ir.GetVector(n);
const IR::U128 reg_m = ir.GetVector(m);
const IR::U128 result = U ? ir.VectorUnsignedSaturatedSub(esize, reg_n, reg_m) : ir.VectorSignedSaturatedSub(esize, reg_n, reg_m);
ir.SetVector(d, result);
return true;
}
} // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_arm.h
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@@ -446,6 +446,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VBIT(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VHSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VQSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
// Advanced SIMD two register, miscellaneous
bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm);

6
src/frontend/A64/translate/impl/simd_three_same.cpp
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@@ -335,7 +335,7 @@ bool SaturatingArithmeticOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Ve
const IR::U128 operand1 = v.V(datasize, Vn);
const IR::U128 operand2 = v.V(datasize, Vm);
const auto result = [&] {
const IR::U128 result = [&] {
if (sign == Signedness::Signed) {
if (op == Operation::Add) {
return v.ir.VectorSignedSaturatedAdd(esize, operand1, operand2);
@@ -351,9 +351,7 @@ bool SaturatingArithmeticOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Ve
return v.ir.VectorUnsignedSaturatedSub(esize, operand1, operand2);
}();
v.ir.OrQC(result.overflow);
v.V(datasize, Vd, result.result);
v.V(datasize, Vd, result);
return true;
}

121
src/frontend/ir/ir_emitter.cpp
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@@ -635,83 +635,66 @@ ResultAndOverflow<U32> IREmitter::UnsignedSaturation(const U32& a, size_t bit_si
return {result, overflow};
}
ResultAndOverflow<U128> IREmitter::VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
const auto result = [&]{
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd8, a, b);
case 16:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd16, a, b);
case 32:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd32, a, b);
case 64:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd64, a, b);
default:
UNREACHABLE();
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
U128 IREmitter::VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd8, a, b);
case 16:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd16, a, b);
case 32:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd32, a, b);
case 64:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd64, a, b);
default:
UNREACHABLE();
}
}
ResultAndOverflow<U128> IREmitter::VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
const auto result = [&]{
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorSignedSaturatedSub8, a, b);
case 16:
return Inst<U128>(Opcode::VectorSignedSaturatedSub16, a, b);
case 32:
return Inst<U128>(Opcode::VectorSignedSaturatedSub32, a, b);
case 64:
return Inst<U128>(Opcode::VectorSignedSaturatedSub64, a, b);
default:
UNREACHABLE();
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
U128 IREmitter::VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorSignedSaturatedSub8, a, b);
case 16:
return Inst<U128>(Opcode::VectorSignedSaturatedSub16, a, b);
case 32:
return Inst<U128>(Opcode::VectorSignedSaturatedSub32, a, b);
case 64:
return Inst<U128>(Opcode::VectorSignedSaturatedSub64, a, b);
default:
UNREACHABLE();
}
}
ResultAndOverflow<U128> IREmitter::VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
const auto result = [&]{
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd8, a, b);
case 16:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd16, a, b);
case 32:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd32, a, b);
case 64:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd64, a, b);
default:
UNREACHABLE();
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
U128 IREmitter::VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd8, a, b);
case 16:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd16, a, b);
case 32:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd32, a, b);
case 64:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd64, a, b);
default:
UNREACHABLE();
}
}
ResultAndOverflow<U128> IREmitter::VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
const auto result = [&]{
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub8, a, b);
case 16:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub16, a, b);
case 32:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub32, a, b);
case 64:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub64, a, b);
default:
UNREACHABLE();
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
U128 IREmitter::VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub8, a, b);
case 16:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub16, a, b);
case 32:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub32, a, b);
case 64:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub64, a, b);
default:
UNREACHABLE();
}
}
ResultAndGE<U32> IREmitter::PackedAddU8(const U32& a, const U32& b) {
const auto result = Inst<U32>(Opcode::PackedAddU8, a, b);
const auto ge = Inst<U32>(Opcode::GetGEFromOp, result);

8
src/frontend/ir/ir_emitter.h
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@@ -166,10 +166,10 @@ public:
ResultAndOverflow<UAny> UnsignedSaturatedSub(const UAny& a, const UAny& b);
ResultAndOverflow<U32> UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to);
ResultAndOverflow<U128> VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
ResultAndOverflow<U128> VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b);
ResultAndOverflow<U128> VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
ResultAndOverflow<U128> VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b);
U128 VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
U128 VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b);
U128 VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
U128 VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b);
ResultAndGE<U32> PackedAddU8(const U32& a, const U32& b);
ResultAndGE<U32> PackedAddS8(const U32& a, const U32& b);

16
src/frontend/ir/microinstruction.cpp
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@@ -421,6 +421,10 @@ bool Inst::WritesToFPSRCumulativeSaturationBit() const {
case Opcode::VectorSignedSaturatedAccumulateUnsigned16:
case Opcode::VectorSignedSaturatedAccumulateUnsigned32:
case Opcode::VectorSignedSaturatedAccumulateUnsigned64:
case Opcode::VectorSignedSaturatedAdd8:
case Opcode::VectorSignedSaturatedAdd16:
case Opcode::VectorSignedSaturatedAdd32:
case Opcode::VectorSignedSaturatedAdd64:
case Opcode::VectorSignedSaturatedDoublingMultiply16:
case Opcode::VectorSignedSaturatedDoublingMultiply32:
case Opcode::VectorSignedSaturatedDoublingMultiplyLong16:
@@ -443,10 +447,18 @@ bool Inst::WritesToFPSRCumulativeSaturationBit() const {
case Opcode::VectorSignedSaturatedShiftLeftUnsigned16:
case Opcode::VectorSignedSaturatedShiftLeftUnsigned32:
case Opcode::VectorSignedSaturatedShiftLeftUnsigned64:
case Opcode::VectorSignedSaturatedSub8:
case Opcode::VectorSignedSaturatedSub16:
case Opcode::VectorSignedSaturatedSub32:
case Opcode::VectorSignedSaturatedSub64:
case Opcode::VectorUnsignedSaturatedAccumulateSigned8:
case Opcode::VectorUnsignedSaturatedAccumulateSigned16:
case Opcode::VectorUnsignedSaturatedAccumulateSigned32:
case Opcode::VectorUnsignedSaturatedAccumulateSigned64:
case Opcode::VectorUnsignedSaturatedAdd8:
case Opcode::VectorUnsignedSaturatedAdd16:
case Opcode::VectorUnsignedSaturatedAdd32:
case Opcode::VectorUnsignedSaturatedAdd64:
case Opcode::VectorUnsignedSaturatedNarrow16:
case Opcode::VectorUnsignedSaturatedNarrow32:
case Opcode::VectorUnsignedSaturatedNarrow64:
@@ -454,6 +466,10 @@ bool Inst::WritesToFPSRCumulativeSaturationBit() const {
case Opcode::VectorUnsignedSaturatedShiftLeft16:
case Opcode::VectorUnsignedSaturatedShiftLeft32:
case Opcode::VectorUnsignedSaturatedShiftLeft64:
case Opcode::VectorUnsignedSaturatedSub8:
case Opcode::VectorUnsignedSaturatedSub16:
case Opcode::VectorUnsignedSaturatedSub32:
case Opcode::VectorUnsignedSaturatedSub64:
return true;
default: