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A32: Implement ASIMD VQSUB instruction

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This commit is contained in:
MerryMage
2020-05-30 16:10:51 +01:00
parent 16ff880f8f
commit f3845cea9a
8 changed files with 157 additions and 184 deletions
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121
src/frontend/ir/ir_emitter.cpp
View File

@@ -635,83 +635,66 @@ ResultAndOverflow<U32> IREmitter::UnsignedSaturation(const U32& a, size_t bit_si
return {result, overflow};
}
ResultAndOverflow<U128> IREmitter::VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
const auto result = [&]{
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd8, a, b);
case 16:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd16, a, b);
case 32:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd32, a, b);
case 64:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd64, a, b);
default:
UNREACHABLE();
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
U128 IREmitter::VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd8, a, b);
case 16:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd16, a, b);
case 32:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd32, a, b);
case 64:
return Inst<U128>(Opcode::VectorSignedSaturatedAdd64, a, b);
default:
UNREACHABLE();
}
}
ResultAndOverflow<U128> IREmitter::VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
const auto result = [&]{
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorSignedSaturatedSub8, a, b);
case 16:
return Inst<U128>(Opcode::VectorSignedSaturatedSub16, a, b);
case 32:
return Inst<U128>(Opcode::VectorSignedSaturatedSub32, a, b);
case 64:
return Inst<U128>(Opcode::VectorSignedSaturatedSub64, a, b);
default:
UNREACHABLE();
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
U128 IREmitter::VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorSignedSaturatedSub8, a, b);
case 16:
return Inst<U128>(Opcode::VectorSignedSaturatedSub16, a, b);
case 32:
return Inst<U128>(Opcode::VectorSignedSaturatedSub32, a, b);
case 64:
return Inst<U128>(Opcode::VectorSignedSaturatedSub64, a, b);
default:
UNREACHABLE();
}
}
ResultAndOverflow<U128> IREmitter::VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
const auto result = [&]{
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd8, a, b);
case 16:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd16, a, b);
case 32:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd32, a, b);
case 64:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd64, a, b);
default:
UNREACHABLE();
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
U128 IREmitter::VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd8, a, b);
case 16:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd16, a, b);
case 32:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd32, a, b);
case 64:
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd64, a, b);
default:
UNREACHABLE();
}
}
ResultAndOverflow<U128> IREmitter::VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
const auto result = [&]{
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub8, a, b);
case 16:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub16, a, b);
case 32:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub32, a, b);
case 64:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub64, a, b);
default:
UNREACHABLE();
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
U128 IREmitter::VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub8, a, b);
case 16:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub16, a, b);
case 32:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub32, a, b);
case 64:
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub64, a, b);
default:
UNREACHABLE();
}
}
ResultAndGE<U32> IREmitter::PackedAddU8(const U32& a, const U32& b) {
const auto result = Inst<U32>(Opcode::PackedAddU8, a, b);
const auto ge = Inst<U32>(Opcode::GetGEFromOp, result);

8
src/frontend/ir/ir_emitter.h
View File

@@ -166,10 +166,10 @@ public:
ResultAndOverflow<UAny> UnsignedSaturatedSub(const UAny& a, const UAny& b);
ResultAndOverflow<U32> UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to);
ResultAndOverflow<U128> VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
ResultAndOverflow<U128> VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b);
ResultAndOverflow<U128> VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
ResultAndOverflow<U128> VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b);
U128 VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
U128 VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b);
U128 VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
U128 VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b);
ResultAndGE<U32> PackedAddU8(const U32& a, const U32& b);
ResultAndGE<U32> PackedAddS8(const U32& a, const U32& b);

16
src/frontend/ir/microinstruction.cpp
View File

@@ -421,6 +421,10 @@ bool Inst::WritesToFPSRCumulativeSaturationBit() const {
case Opcode::VectorSignedSaturatedAccumulateUnsigned16:
case Opcode::VectorSignedSaturatedAccumulateUnsigned32:
case Opcode::VectorSignedSaturatedAccumulateUnsigned64:
case Opcode::VectorSignedSaturatedAdd8:
case Opcode::VectorSignedSaturatedAdd16:
case Opcode::VectorSignedSaturatedAdd32:
case Opcode::VectorSignedSaturatedAdd64:
case Opcode::VectorSignedSaturatedDoublingMultiply16:
case Opcode::VectorSignedSaturatedDoublingMultiply32:
case Opcode::VectorSignedSaturatedDoublingMultiplyLong16:
@@ -443,10 +447,18 @@ bool Inst::WritesToFPSRCumulativeSaturationBit() const {
case Opcode::VectorSignedSaturatedShiftLeftUnsigned16:
case Opcode::VectorSignedSaturatedShiftLeftUnsigned32:
case Opcode::VectorSignedSaturatedShiftLeftUnsigned64:
case Opcode::VectorSignedSaturatedSub8:
case Opcode::VectorSignedSaturatedSub16:
case Opcode::VectorSignedSaturatedSub32:
case Opcode::VectorSignedSaturatedSub64:
case Opcode::VectorUnsignedSaturatedAccumulateSigned8:
case Opcode::VectorUnsignedSaturatedAccumulateSigned16:
case Opcode::VectorUnsignedSaturatedAccumulateSigned32:
case Opcode::VectorUnsignedSaturatedAccumulateSigned64:
case Opcode::VectorUnsignedSaturatedAdd8:
case Opcode::VectorUnsignedSaturatedAdd16:
case Opcode::VectorUnsignedSaturatedAdd32:
case Opcode::VectorUnsignedSaturatedAdd64:
case Opcode::VectorUnsignedSaturatedNarrow16:
case Opcode::VectorUnsignedSaturatedNarrow32:
case Opcode::VectorUnsignedSaturatedNarrow64:
@@ -454,6 +466,10 @@ bool Inst::WritesToFPSRCumulativeSaturationBit() const {
case Opcode::VectorUnsignedSaturatedShiftLeft16:
case Opcode::VectorUnsignedSaturatedShiftLeft32:
case Opcode::VectorUnsignedSaturatedShiftLeft64:
case Opcode::VectorUnsignedSaturatedSub8:
case Opcode::VectorUnsignedSaturatedSub16:
case Opcode::VectorUnsignedSaturatedSub32:
case Opcode::VectorUnsignedSaturatedSub64:
return true;
default: