SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-06 02:26:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

A64: Implement ISB

Browse Source 
Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
This commit is contained in:
Lioncash
2018-08-17 20:20:42 -04:00
committed by MerryMage
parent be53e356a2
commit f3f60cd179
9 changed files with 45 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View File

@@ -64,7 +64,7 @@ INST(SEVL, "SEVL", "11010
INST(CLREX, "CLREX", "11010101000000110011MMMM01011111")
INST(DSB, "DSB", "11010101000000110011MMMM10011111")
INST(DMB, "DMB", "11010101000000110011MMMM10111111")
//INST(ISB, "ISB", "11010101000000110011MMMM11011111")
INST(ISB, "ISB", "11010101000000110011MMMM11011111")
//INST(SYS, "SYS", "1101010100001oooNNNNMMMMooottttt")
INST(MSR_reg, "MSR (register)", "110101010001poooNNNNMMMMooottttt")
//INST(SYSL, "SYSL", "1101010100101oooNNNNMMMMooottttt")

4
src/frontend/A64/ir_emitter.cpp
View File

@@ -57,6 +57,10 @@ void IREmitter::DataMemoryBarrier() {
Inst(Opcode::A64DataMemoryBarrier);
}
void IREmitter::InstructionSynchronizationBarrier() {
Inst(Opcode::A64InstructionSynchronizationBarrier);
}
IR::U32 IREmitter::GetCNTFRQ() {
return Inst<IR::U32>(Opcode::A64GetCNTFRQ);
}

1
src/frontend/A64/ir_emitter.h
View File

@@ -45,6 +45,7 @@ public:
void DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value);
void DataSynchronizationBarrier();
void DataMemoryBarrier();
void InstructionSynchronizationBarrier();
IR::U32 GetCNTFRQ();
IR::U64 GetCNTPCT(); // TODO: Ensure sub-basic-block cycle counts are updated before this.
IR::U32 GetCTR();

7
src/frontend/A64/translate/impl/system.cpp
View File

@@ -71,6 +71,13 @@ bool TranslatorVisitor::DMB(Imm<4> /*CRm*/) {
return true;
}
bool TranslatorVisitor::ISB(Imm<4> /*CRm*/) {
ir.InstructionSynchronizationBarrier();
ir.SetPC(ir.Imm64(ir.current_location->PC() + 4));
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
bool TranslatorVisitor::MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
const auto sys_reg = concatenate(Imm<1>{1}, o0, op1, CRn, CRm, op2).ZeroExtend<SystemRegisterEncoding>();
switch (sys_reg) {

27
src/frontend/ir/microinstruction.cpp
View File

@@ -395,19 +395,20 @@ bool Inst::IsCoprocessorInstruction() const {
}
bool Inst::MayHaveSideEffects() const {
return op == Opcode::PushRSB ||
op == Opcode::A64SetCheckBit ||
op == Opcode::A64DataCacheOperationRaised ||
op == Opcode::A64DataSynchronizationBarrier ||
op == Opcode::A64DataMemoryBarrier ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
return op == Opcode::PushRSB ||
op == Opcode::A64SetCheckBit ||
op == Opcode::A64DataCacheOperationRaised ||
op == Opcode::A64DataSynchronizationBarrier ||
op == Opcode::A64DataMemoryBarrier ||
op == Opcode::A64InstructionSynchronizationBarrier ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
IsCoprocessorInstruction();
}

1
src/frontend/ir/opcodes.inc
View File

@@ -66,6 +66,7 @@ A64OPC(ExceptionRaised, T::Void, T::U64,
A64OPC(DataCacheOperationRaised, T::Void, T::U64, T::U64 )
A64OPC(DataSynchronizationBarrier, T::Void, )
A64OPC(DataMemoryBarrier, T::Void, )
A64OPC(InstructionSynchronizationBarrier, T::Void, )
A64OPC(GetCNTFRQ, T::U32, )
A64OPC(GetCNTPCT, T::U64, )
A64OPC(GetCTR, T::U32, )