SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-05 10:16:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant

Browse Source
This commit is contained in:
MerryMage
2018-07-22 18:19:16 +01:00
parent bde58b04d4
commit f837ce8e78
2 changed files with 11 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View File

@@ -397,7 +397,7 @@ INST(FCVTPU_2, "FCVTPU (vector)", "01111
//INST(FCVTZU_int_1, "FCVTZU (vector, integer)", "0111111011111001101110nnnnnddddd")
INST(FCVTZU_int_2, "FCVTZU (vector, integer)", "011111101z100001101110nnnnnddddd")
//INST(FRSQRTE_1, "FRSQRTE", "0111111011111001110110nnnnnddddd")
//INST(FRSQRTE_2, "FRSQRTE", "011111101z100001110110nnnnnddddd")
INST(FRSQRTE_2, "FRSQRTE", "011111101z100001110110nnnnnddddd")
// Data Processing - FP and SIMD - Scalar three same extra
//INST(SQRDMLAH_vec_1, "SQRDMLAH (vector)", "01111110zz0mmmmm100001nnnnnddddd")