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A32: Implement ASIMD VCEQ (integer)

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This commit is contained in:
Lioncash
2020-06-20 17:02:36 -04:00
committed by merry
parent 7276993352
commit faefb264a6
3 changed files with 8 additions and 1 deletions
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6
src/frontend/A32/translate/impl/asimd_three_same.cpp
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@@ -89,6 +89,8 @@ bool IntegerComparison(ArmTranslatorVisitor& v, bool U, bool D, size_t sz, size_
case Comparison::GE:
return U ? v.ir.VectorGreaterEqualUnsigned(esize, reg_n, reg_m)
: v.ir.VectorGreaterEqualSigned(esize, reg_n, reg_m);
case Comparison::EQ:
return v.ir.VectorEqual(esize, reg_n, reg_m);
default:
return IR::U128{};
}
@@ -411,6 +413,10 @@ bool ArmTranslatorVisitor::asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, b
return true;
}
bool ArmTranslatorVisitor::asimd_VCEQ_reg(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
return IntegerComparison(*this, false, D, sz, Vn, Vd, N, Q, M, Vm, Comparison::EQ);
}
bool ArmTranslatorVisitor::asimd_VMLA(bool op, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (sz == 0b11) {
return UndefinedInstruction();

1
src/frontend/A32/translate/impl/translate_arm.h
View File

@@ -472,6 +472,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VRSHL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMAX(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, bool op, size_t Vm);
bool asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VCEQ_reg(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMLA(bool op, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VPADD(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);