SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-26 18:38:43 +00:00
Code Issues Packages Projects Releases Wiki Activity

A32: Implement ASIMD VABA

Browse Source
This commit is contained in:
Lioncash
2020-06-20 21:29:59 -04:00
committed by merry
parent bdb92f7055
commit fc1633a2ea
3 changed files with 27 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
src/frontend/A32/translate/impl/asimd_three_same.cpp
View File

@@ -306,6 +306,31 @@ bool ArmTranslatorVisitor::asimd_VCGE_reg(bool U, bool D, size_t sz, size_t Vn,
return IntegerComparison(*this, U, D, sz, Vn, Vd, N, Q, M, Vm, Comparison::GE);
}
bool ArmTranslatorVisitor::asimd_VABA(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (sz == 0b11) {
return UndefinedInstruction();
}
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto n = ToVector(Q, Vn, N);
const auto reg_d = ir.GetVector(d);
const auto reg_m = ir.GetVector(m);
const auto reg_n = ir.GetVector(n);
const auto absdiff = U ? ir.VectorUnsignedAbsoluteDifference(esize, reg_m, reg_n)
: ir.VectorSignedAbsoluteDifference(esize, reg_m, reg_n);
const auto result = ir.VectorAdd(esize, reg_d, absdiff);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VADD_int(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();

1
src/frontend/A32/translate/impl/translate_arm.h
View File

@@ -464,6 +464,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VQSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VCGT_reg(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VCGE_reg(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VABA(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VADD_int(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VSUB_int(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VSHL_reg(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);