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3,080 Commits 2 Branches 0 Tags 34 MiB
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2603 Commits

Author SHA1 Message Date
Merry
02d3a5a242 emit_arm64_a32: Implement A32OrQFlag 2022-10-18 15:04:30 +01:00
Merry
a50eb6cf34 emit_arm64_packed: Implement PackedAddS8 2022-10-18 15:04:30 +01:00
Merry
619adce84f emit_arm64_packed: Implement PackedAddU8 2022-10-18 15:04:30 +01:00
Merry
8f1f1c8f0b emit_arm64_packed: Implement {Get,Set}GEFlags 2022-10-18 15:04:30 +01:00
Merry
2dce8ea5a8 emit_arm64_data_processing: Fix MostSignificantWord 2022-10-18 15:04:30 +01:00
Merry
3d420e34ae emit_arm64_data_processing: Fix LogicalShiftRight32 for immediate shift = 32 2022-10-18 15:04:30 +01:00
Merry
a5f3164c38 backend/arm64/reg_alloc: Handle immediates in DefineAsExisting 2022-10-18 15:04:30 +01:00
Merry
277f7a76e9 arm64: Stub PushRSB 2022-10-18 15:04:30 +01:00
Merry
ef137dd8b9 emit_arm64_data_processing: Correct ArithmeticShiftRight32 2022-10-18 15:04:30 +01:00
Merry
70d9137859 backend/arm64/reg_alloc: Handle immediates in PrepareForCall 2022-10-18 15:04:30 +01:00
Merry
187f89951d emit_arm64_data_processing: Implement Mul 2022-10-18 15:04:30 +01:00
Merry
bf55920ce9 backend/arm64/reg_alloc: Support multiple locks on a location 2022-10-18 15:04:30 +01:00
Merry
6bcfaee1f4 emit_arm64_data_processing: Implement LogicalShiftRight32 2022-10-18 15:04:30 +01:00
Merry
7840caef6e emit_arm64_data_processing: Fix bug in EmitBitOp 2022-10-18 15:04:30 +01:00
Merry
02cfbb8b0b backend/arm64/reg_alloc: Generate immediates when required 2022-10-18 15:04:30 +01:00
Merry
bdb41be0c5 emit_arm64_data_processing: Implement ZeroExtend 2022-10-18 15:04:30 +01:00
Merry
7ed217ff77 emit_arm64_data_processing: Implement SignExtend 2022-10-18 15:04:30 +01:00
Merry
777d9a1045 emit_arm64_data_processing: Implement ByteReverse 2022-10-18 15:04:30 +01:00
Merry
156bcecb02 emit_arm64_data_processing: Implement ArithmeticShiftRight32 2022-10-18 15:04:30 +01:00
Merry
a6e761daa9 emit_arm64_a32: Fix CheckBit 2022-10-18 15:04:30 +01:00
Merry
95ae21bd41 backend/arm64: Fix Sub 2022-10-18 15:04:30 +01:00
Merry
46f4063952 backend/arm64: Implement Not 2022-10-18 15:04:30 +01:00
Merry
6ad7758165 backend/arm64: Implement AndNot 2022-10-18 15:04:30 +01:00
Merry
fcd2bd600e backend/arm64: Implement Or 2022-10-18 15:04:30 +01:00
Merry
4cff0d9977 backend/arm64: Implement Eor 2022-10-18 15:04:30 +01:00
Merry
4e3fd70f6e backend/arm64: Implement And64 2022-10-18 15:04:30 +01:00
Merry
129af4f6b4 backend/arm64: Implement A32SetCpsrNZ 2022-10-18 15:04:30 +01:00
Merry
7056913b6b backend/arm64: Implement And32 2022-10-18 15:04:30 +01:00
Merry
f97b520221 backend/arm64: Implement RotateRight32 2022-10-18 15:04:30 +01:00
Merry
6885f9a6d8 backend/arm64: Invalidation fixes 2022-10-18 15:04:30 +01:00
Merry
eaf87ec1e4 backend/arm64: Simple implementation of memory read/write 2022-10-18 15:04:30 +01:00
Merry
77634509b5 arm64/abi: Deduplicate register code 2022-10-18 15:04:30 +01:00
Merry
f3bf27c816 backend/arm64: Implement Devirtualize 2022-10-18 15:04:30 +01:00
Merry
2e72d69268 backend/arm64: ABI 2022-10-18 15:04:30 +01:00
Merry
f74a5f262f backend/arm64/reg_alloc: RAReg is non-copyable and non-moveable 2022-10-18 15:04:30 +01:00
Merry
3a3b43b963 backend/arm64: Implement A32ClearExclusive 2022-10-18 15:04:30 +01:00
Merry
9bdff6a9aa constant_propagation_pass: Shift with non-zero value does not require c flag as input 2022-10-18 15:04:30 +01:00
Merry
5a864f41c6 backend/arm64/reg_alloc: Implement DefineAsRegister 2022-10-18 15:04:30 +01:00
Merry
16701ae6d5 backend/arm64/reg_alloc: Use NZCV instead of magic numbers 2022-10-18 15:04:30 +01:00
Merry
c2ff75e29c backend/arm64: Implement Sub 2022-10-18 15:04:30 +01:00
Merry
8ac57bd6ed backend/arm64/reg_alloc: Assert on bad RAReg 2022-10-18 15:04:30 +01:00
Merry
78bc0812b9 backend/arm64/reg_alloc: More flag handling 2022-10-18 15:04:30 +01:00
Merry
21601764de backend/arm64: Implement Add 2022-10-18 15:04:30 +01:00
Merry
679efb9c44 backend/arm64: Implement A32SetCpsrNZCV 2022-10-18 15:04:30 +01:00
Merry
67df13f886 backend/arm64: Update for new C flag representation 2022-10-18 15:04:30 +01:00
Merry
d69582f548 backend/arm64/reg_alloc: Tidy up HostLocInfo 2022-10-18 15:04:30 +01:00
Merry
01f28facbd abi: Add Rscratch{0,1} 2022-10-18 15:04:30 +01:00
Merry
8b41755db0 ir_emitter: Remove unused ResultAndCarryAndOverflow structure 2022-10-18 15:04:30 +01:00
Merry
b6bb94872a backend/arm64: Implement IsZero64 2022-10-18 15:04:30 +01:00
Merry
3821c4a16b backend/arm64: Implement MostSignificantWord 2022-10-18 15:04:30 +01:00
Merry
ec3c597591 backend/arm64: Implement LeastSignificantByte 2022-10-18 15:04:30 +01:00
Merry
a33d186fea backend/arm64: Implement LeastSignificantHalf 2022-10-18 15:04:30 +01:00
Merry
163ed9b185 backend/arm64: Implement LeastSignificantWord 2022-10-18 15:04:30 +01:00
Merry
7c86b06233 backend/arm64: Implement Pack2x64To1x128 2022-10-18 15:04:30 +01:00
Merry
98806139a5 backend/arm64/reg_alloc: Argument HostLoc location 2022-10-18 15:04:30 +01:00
Merry
fe4e864e4c backend/arm64: Implement Pack2x32To1x64 2022-10-18 15:04:30 +01:00
Merry
ff9b92c791 backend/arm64: Implement NZCVFromPackedFlags 2022-10-18 15:04:30 +01:00
Merry
7ea97f7629 backend/arm64: Implement GetLowerFromOp 2022-10-18 15:04:30 +01:00
Merry
92026a456a backend/arm64: Implement GetUpperFromOp 2022-10-18 15:04:30 +01:00
Merry
8c4ea10a38 backend/arm64: Implement GetNZCVFromOp 2022-10-18 15:04:30 +01:00
Merry
e34749336a backend/arm64: Implement GetGEFromOp 2022-10-18 15:04:30 +01:00
Merry
fbcbc1d90d backend/arm64: Implement GetOverflowFromOp 2022-10-18 15:04:30 +01:00
Merry
fb3b828158 backend/arm64: Implement Identity 2022-10-18 15:04:30 +01:00
Merry
97ba8a0f14 backend/arm64: Implement Void 2022-10-18 15:04:30 +01:00
Merry
2a24bb2c1e backend/arm64: Implement Breakpoint 2022-10-18 15:04:30 +01:00
Merry
3a11467220 backend/arm64: Stub all IR instruction implementations 2022-10-18 15:04:30 +01:00
Merry
402abf5ea3 backend/arm64: Implement A32GetExtendedRegister 2022-10-18 15:04:30 +01:00
Merry
84cad9f831 backend/arm64: Implement A32SetCheckBit 2022-10-18 15:04:30 +01:00
Merry
52a46d841b backend/arm64: Implement A32BXWritePC 2022-10-18 15:04:30 +01:00
Merry
67dc7f2e4e backend/arm64: Implement A32UpdateUpperLocationDescriptor 2022-10-18 15:04:30 +01:00
Merry
00ad84b7ab backend/arm64: Initial implementation of terminals 2022-10-18 15:04:30 +01:00
Merry
80c89401b9 a32_address_space: Add StackLayout to stack 2022-10-18 15:04:30 +01:00
Merry
9b2391ec7b backend/arm64/reg_alloc: Implement AssertNoMoreUses 2022-10-18 15:04:30 +01:00
Merry
8e6467bf45 backend/arm64/reg_alloc: Add flag handling 2022-10-18 15:04:30 +01:00
Merry
77436bbbbb backend/arm64: Toy implementation of enough to execute LSLS 2022-10-18 15:04:30 +01:00
Merry
7e046357ff backend/arm64: Initial implementation of register allocator 2022-10-18 15:04:30 +01:00
Merry
3bf2b0aba9 backend/arm64: Adjust how relocations are stored 2022-10-18 15:04:30 +01:00
Merry
e0f091b6a6 backend/arm64: void* -> CodePtr 2022-10-18 15:04:30 +01:00
Merry
f6e80f1e0e backend/arm64: First dummy code execution 2022-10-18 15:04:30 +01:00
Merry
d877777c50 backend/arm64: Initial framework 2022-10-18 15:04:30 +01:00
Wunkolo
e886bfb7c1 backend/x64: Fix FixupLUT argument order 
The last two arguments(fixup response response for finite values) are
neg-pos, not pos-neg. Found this out while re-using this function for
some math stuff. Thankfully nothing currently uses this fixup response
at the moment.
 2022-09-30 23:10:21 +01:00
Merry
af51845a53 decoder_detail: Workaround #708 2022-09-02 21:16:43 +01:00
Bart Ribbers
e49fee0ca1 block_of_code: rename PAGE_SIZE to DYNARMIC_PAGE_SIZE to prevent use of reserved name 
PAGE_SIZE is a kernel symbol and depending on the libc in use, it will
"leak". In this case dynarmic was using it's own PAGE_SIZE and in
combination with the Musl libc the compiler would complain it was overwriting
the kernel symbol
 2022-08-25 23:32:18 +01:00
Merry
bf422a190a decoder_detail: Simplify DYNARMIC_DECODER_GET_MATCHER 2022-08-21 18:22:14 +01:00
Merry
c60fd3f0ac block_of_code: Fix running under Rosetta 
Rosetta doesn't have accurate emulation of the sahf instruction
 2022-08-05 23:43:01 +01:00
Merry
a38966a874 block_of_code: Extract flag loading into a function 
LoadRequiredFlagsForCondFromRax
 2022-08-05 23:42:19 +01:00
Merry
d7bd5bb7a7 emit_x64: Use movzx(eax, ah) instead of emitting byte equivalent 
Emission fixed in xbyak v6.61
 2022-07-31 17:52:35 +01:00
Merry
f33c6f062b Revert "block_of_code: Refactor MConst to Xmm{B}Const" 
This reverts commit 5d9b720189.

Obscure bugs resulting from this commit due to assumptions regarding zero-extension of higher bits.
 2022-07-27 20:31:08 +01:00
Merry
fbdcfeab99 emit_x64_packed: Do not use XmmBConst here 
Broadcasting is inappropriate
 2022-07-27 20:14:49 +01:00
Merry
1f51dceb60 Update for fmt 9.0.0 2022-07-26 11:20:47 +01:00
Merry
82d71b850e a32_emit_x64: Bugfix for A32GetCpsr for non-FastBMI2 
Incorrect loading of E and T flags
 2022-07-26 10:44:30 +01:00
Merry
a2b3199adf Convert NZCV to C flag where able 2022-07-23 11:46:07 +01:00
Merry
6bcc424e1a emit_x64_vector: Ensure FPSR.QC is set even if output is invalidated 2022-07-20 19:44:39 +01:00
Merry
34cb465fc7 translate_thumb: IsThumb16: Mask not required 2022-07-20 17:34:31 +01:00
Merry
72c87d11e4 a32_get_set_elimination_pass: Correct insertion point 2022-07-20 16:53:48 +01:00
Merry
da2b1c5724 a32_get_set_elimination_pass: Convert NZ to NZC 2022-07-20 16:45:14 +01:00
Merry
6f106602ba a32_get_set_elimination_pass: Add option to disable NZC -> NZ conversion 2022-07-20 16:42:39 +01:00
Merry
52aa68c31c backend/x64: Fixup NZ flag emission 2022-07-20 14:58:28 +01:00
Merry
b97147e187 a32_get_set_elimination_pass: Reduce NZC to 00C 2022-07-20 14:44:33 +01:00
Merry
03dcc3fa50 a32_get_set_elimination_pass: Reduce NZC to NZ where possible 2022-07-20 14:08:41 +01:00