8 Commits

Author	SHA1	Message	Date
MerryMage	896cb46c89	asimd_*: Standardize order of n and m to reduce confusion	2020-07-04 11:04:10 +01:00
Lioncash	b5df8d1ef8	A32: Implement ASIMD VQDMULL (scalar)	2020-06-23 18:19:42 +01:00
Lioncash	20a2bf29fc	A32: Implement ASIMD VQRDMULH (scalar)	2020-06-23 18:19:42 +01:00
Lioncash	ab5efe8632	A32: Implement ASIMD VQDMULH (scalar)	2020-06-23 18:19:42 +01:00
MerryMage	33a81dae68	asimd: VEXT was being shadowed	2020-06-21 13:12:19 +01:00
MerryMage	9cc11681dc	A32: Implement ASIMD VMLAL, VMLSL, VMULL (scalar)	2020-06-21 10:31:30 +01:00
Lioncash	230fa02648	A32: Implement ASIMD VMLA/VMLS (scalar) ... While we're at it, we can join the implementation of VMUL into a common function.	2020-06-21 07:51:17 +01:00
MerryMage	715db8381f	A32: Implement ASIMD VMUL (scalar)	2020-06-20 20:34:08 +01:00