8 Commits

Author	SHA1	Message	Date
Lioncash	4b371c0445	A32: Implement ASIMD VREV{16, 32, 64}	2020-06-17 10:21:59 +01:00
Lioncash	6dd2c94095	A32: Implement ASIMD VABS ... Very similar to VNEG in that the only thing that differs is the function called.	2020-06-16 22:42:18 +01:00
Lioncash	aabd0d824d	A32: Add immediate creation helper ... Provides the same helper function that exists within the A64 frontend for creating immediate values.	2020-06-16 09:54:28 +01:00
Lioncash	93ed3441b7	A32: Implement ASIMD VCLS/VCLZ/VCNT	2020-06-16 09:54:28 +01:00
Lioncash	15b3de95e4	A32: Implement VNEG	2020-06-16 01:53:21 +01:00
MerryMage	f8062345bb	asimd_two_regs_misc: Use {Get,Set}Vector	2020-05-28 21:05:30 +01:00
Lioncash	c4a4bdd7de	frontend: Relocate ExtReg handling to types.h ... Same behavior, but deduplicates the code being placed across several files	2020-05-24 23:55:47 +01:00
Lioncash	659d78c9c4	A32: Implement ASIMD VSWP ... A trivial one to implement, this just swaps the contents of two registers in place.	2020-05-22 19:43:24 +01:00