17 Commits

Author	SHA1	Message	Date
Fernando Sahmkow	677f62dd6f	Implement SHSUB8 and SHSUB16 (#74) ... * Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16	2016-12-22 12:02:24 +00:00
FernandoS27	8919265d2c	Implement SADD8, SADD16, SSUB8, SSUB16, USUB16	2016-12-20 21:52:38 +00:00
FernandoS27	3f6ecfe245	Implemented USAD8 and USADA8	2016-12-20 21:52:38 +00:00
MerryMage	b178ab3bec	Replace (void)(...); idiom with UNUSED macro	2016-12-15 21:36:05 +00:00
MerryMage	546198d603	translate_arm: Mark arguments as unused	2016-12-15 20:52:20 +00:00
MerryMage	52e1445f43	Implement USUB8	2016-12-05 00:29:15 +00:00
MerryMage	1a1646d962	Implement UADD8	2016-12-04 20:52:33 +00:00
Merry	0ff8c375af	Implement UHSUB8 and UHSUB16 (#48)	2016-11-26 18:27:21 +00:00
Merry	cb17f9a3ed	Implement SHADD8 and SHADD16 (#47)	2016-11-26 18:12:29 +00:00
MerryMage	c0c1bb1094	Implemented UHADD16	2016-11-26 11:28:20 +00:00
Sebastian Valle	4d44474ad4	Implemented the ARM UHADD8 instruction. (#45) ... The x64 implementation uses the SSSE3 instruction PSHUFB. A non-SSE fallback is provided in case the CPU doesn't support it.	2016-11-25 20:32:22 +00:00
MerryMage	fe15cbd50e	translate_arm/parallel: Detect UNPREDICTABLE instructions	2016-08-19 00:59:07 +01:00
bunnei	8e68e6fdd9	TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.	2016-08-12 19:00:44 +01:00
bunnei	4b09c0d032	TranslateArm: Implement QADD8 and UQADD8.	2016-08-12 19:00:44 +01:00
bunnei	127fbe99cb	TranslateArm: Implement QSUB8.	2016-08-12 19:00:44 +01:00
bunnei	86fe29c6d2	TranslateArm: Implement UQSUB8.	2016-08-12 19:00:44 +01:00
MerryMage	a875c0c720	TranslateArm: Stub more ARM instructions	2016-08-02 21:59:33 +01:00