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2378 Commits

Author SHA1 Message Date
MerryMage
0a98e5d3d7 exception_handler_*: Simplify message for case when exception is not our fault 2021-05-30 22:22:02 +01:00
MerryMage
9815502fee emit_x64_data_processing: operand in EmitExtractRegister is not modified 2021-05-30 22:18:21 +01:00
Markus Wick
36c3b289a0 fixup! a64/fastmem: Implement fastmem on 128 bit memory access. 2021-05-28 22:14:09 +01:00
Markus Wick
e82685223a a64/fastmem: Implement fastmem on 128 bit memory access. 2021-05-28 18:49:31 +01:00
Markus Wick
ff01b1c6f9 a64/fastmem: Only generate abort handler if needed. 
If fastmem fails, we call the callback from the signal handler. So this callback proxy in slowmem won't be used ever.
 2021-05-28 18:49:31 +01:00
MerryMage
709773dcf1 a64_emit_x64: Implement fastmem for A64 frontend for 8-64 bit reads/writes 2021-05-28 18:49:31 +01:00
Merry
bbffae2f96 emit_x64_vector_saturation: AVX implementation of EmitVectorSignedSaturated 2021-05-28 15:34:49 +01:00
Merry
56e3bf57d2 emit_x64_vector_saturated: Consolidate unsigned operations into EmitVectorUnsignedSaturated 2021-05-28 15:34:49 +01:00
Merry
a76e8c8827 emit_x64_vector_saturation: Reduce esize noise in EmitVectorSignedSaturated 2021-05-28 15:34:49 +01:00
Merry
de31caca49 emit_x64_vector_saturation: AVX implementation of EmitVectorUnsignedSaturatedSub32 2021-05-28 15:34:49 +01:00
Merry
b46e6a24dc emit_x64_vector_saturation: AVX implementation of EmitVectorUnsignedSaturatedAdd32 2021-05-28 15:34:49 +01:00
Merry
d087ef42b9 emit_x64_vector_saturation: AVX implementation of EmitVectorUnsignedSaturatedSub32 2021-05-28 15:34:49 +01:00
Merry
0a232a6fbf emit_x64_vector_saturation: AVX2 implementation of EmitVectorUnsignedSaturatedAdd64 2021-05-28 15:34:49 +01:00
Wunkolo
57601f064b emit_x64_vector_saturation: AVX512 implementation of EmitVectorSignedSaturated 2021-05-28 15:34:49 +01:00
Wunkolo
332c26d432 emit_x64_vector_saturation: AVX512 implementation of VectorUnsignedSaturated{Add,Sub}{32,64} 2021-05-28 15:34:49 +01:00
Wunkolo
fa8cc1ac36 backend/x64: Add constants 
Used to redefine x86 assembly-constants without
including platform-dependent headers such as `immintrin.h`.

Currently includes vpcmp constants as well as ternary logic
utility-terms.

Removes `immintrin.h` requirement from emit_x64_vector_saturation
and updates our usage of `vpcmp` and `vpternlog` with the new constants
 2021-05-28 14:13:11 +01:00
MerryMage
f6f8024fb5 a32_emit_x64: Dump x64 disassembly upon fastmem patch failure 2021-05-25 21:57:29 +01:00
MerryMage
4256d21481 common: Add x64_disassemble 2021-05-25 21:56:59 +01:00
MerryMage
17ae7f9ce1 IR: Implement IR instruction CallHostFunction 2021-05-23 15:44:57 +01:00
Wunkolo
3c693f2576 emit_x64_vector: AVX512VBMI implementation of EmitVectorTableLookup128 
Also adds AVX512VBMI detection to host_feature
 2021-05-22 22:48:31 +01:00
Wunkolo
37b24ee29e emit_x64_vector: AVX512{VL+BW} implementation of EmitVectorTableLookup128 
Based off of the SSE41 implementation but utilizing
embedded broadcasting, mask registers, and
the special zero-mask to default-initialize out-of-bound
indices to zero in the `is_defaults_zero` case.
 2021-05-22 22:47:21 +01:00
MerryMage
53493b2024 Add .clang-format file 
Using clang-format version 12.0.0
 2021-05-22 15:07:02 +01:00
MerryMage
51b155df92 A32: Introduce PreCodeTranslationHook 2021-05-22 14:16:10 +01:00
Merry
714216fd0e Consolidate all source files into src/ directory 2021-05-19 17:41:59 +01:00
MerryMage
c6ecc835b6 ASIMD: Implement VCVT (between half-precision and single-precision) 2021-05-16 23:48:29 +01:00
MerryMage
9de58f2875 assert: Check for unreachable code if DYNARMIC_IGNORE_ASSERTS isn't enabled 2021-05-16 21:46:44 +01:00
MerryMage
5bf74b5f04 reg_alloc: Determine size of spill slot with sizeof 2021-05-16 21:46:10 +01:00
MerryMage
b6bff56523 translate_thumb: Update current_instruction_size in TranslateSingleThumbInstruction 2021-05-16 10:31:30 +01:00
Wunkolo
2c0be5e18c emit_x64_vector: AVX512 Implementation of EmitVectorNarrow{32,64} 
Includes a new test case with the XTN instruction to verify
the implementation
 2021-05-16 10:02:49 +01:00
MerryMage
1643e8f3c6 translate_thumb: VFP/ASIMD conflict with coprocessor instructions 2021-05-15 20:54:35 +01:00
Wunkolo
105b464bc1 backend/x64: Implement HostFeature 2021-05-14 21:20:21 +01:00
MerryMage
b93ae62acf thumb32: Add coprocessor instructions 2021-05-13 18:15:35 +01:00
MerryMage
5ebe11c329 reg_alloc: Inform RegAlloc about rsp changes 2021-05-07 12:47:55 +01:00
MerryMage
05a6b5f623 translate_thumb: Permit ASIMD element or structure load/store instructions to be translated 2021-05-07 12:47:55 +01:00
sunho
cb79bfa1dc thumb32: Support setflags in shift reg instructions 2021-05-05 11:47:49 +01:00
MerryMage
075fdeaee0 thumb32: Add Rn argument to ADD/SUB (Plain Binary Immediate) 2021-05-05 11:47:49 +01:00
MerryMage
ebe44dab7a stack_layout: Ignore warning C4324 for StackLayout 
We expect the structure to be padded
 2021-05-04 16:26:28 +01:00
MerryMage
462c884685 frontend/A32: Correct more IT state 2021-05-04 16:25:24 +01:00
MerryMage
c5f5c1d40f frontend: Standardize emitted IR for exception raising 2021-05-04 16:14:26 +01:00
MerryMage
3b2c6afdc2 backend/x64: Move cycles_remaining and cycles_to_run from JitState to stack 2021-05-04 14:40:13 +01:00
MerryMage
d6592c7142 Remove ExceptionalExit hack 2021-05-04 14:40:13 +01:00
MerryMage
030ff82ba8 backend/x64: Move check_bit from JitState to stack 2021-05-04 14:40:13 +01:00
MerryMage
a1950d1d2f backend/x64: Move save_host_MXCSR from JitState to stack 2021-05-04 14:19:05 +01:00
MerryMage
ddbc50cee0 backend/x64: Move spill from JitState onto the stack 2021-05-04 14:18:44 +01:00
MerryMage
f8d8ea0deb thumb32: Implement MRS (register) 2021-05-04 12:43:51 +01:00
MerryMage
61333917a4 thumb32: Implement MRS (register) 2021-05-04 12:43:38 +01:00
MerryMage
a5a210a9a5 T32: Add ASIMD instructions 2021-05-04 00:09:55 +01:00
MerryMage
d1e62b9993 T32: Add VFP instructions 2021-05-04 00:09:55 +01:00
MerryMage
cd837c5b37 A32: Merge ArmTranslateVistor and ThumbTranslateVisitor 2021-05-04 00:09:55 +01:00
MerryMage
6d292e3eac decoder: Ensure more compiler-time computation 
Replace with consteval when C++20 hits
 2021-05-03 13:09:51 +01:00
MerryMage
795b9bea9a Remove ChangeProcessorID hack 
* No library users require this hack any longer.
 2021-05-01 20:33:14 +01:00
MerryMage
6759942b56 emit_x64_data_processing: Correct bug in ArithmeticShiftRight64 
This branch of this implementation is unused, and thus has not been tested.
 2021-04-27 18:51:23 +01:00
MerryMage
68088c277c emit_x64_data_processing: Reduce codesize of RotateRight32 for carry case 2021-04-26 21:57:22 +01:00
MerryMage
f77b98de36 emit_x64_data_processing: Reduce codesize of ArithmeticShiftRight32 for carry case 2021-04-26 21:57:08 +01:00
MerryMage
a2a687f208 emit_x64_data_processing: Reduce codesize of LogicalShiftRight32 for carry case 2021-04-26 21:56:42 +01:00
MerryMage
58ff457339 emit_x64_data_processing: Reduce codesize of LogicalShiftLeft32 for carry case 2021-04-26 21:35:06 +01:00
MerryMage
510862e50c backend/x64: Change V flag testing to cmp instead of add 
Prefer a non-destructive read to a destructive read.
 2021-04-26 00:26:28 +01:00
MerryMage
3f74a839b9 emit_x64_floating_point: Optimize 64-bit EmitFPRSqrtEstimate 2021-04-26 00:26:28 +01:00
MerryMage
7bc9e36ed7 emit_x64_floating_point: Optimize 32-bit EmitFPRSqrtEstimate 2021-04-26 00:26:28 +01:00
MerryMage
e19f898aa2 ir: Reorganize to new top level folder 2021-04-21 22:22:07 +01:00
MerryMage
5bec200c36 block_of_code: Add santiy check that far_code_offset < total_code_size 2021-04-21 18:26:26 +01:00
MerryMage
08ed8b4a11 abi: Consolodate ABI information into one place 2021-04-21 18:25:04 +01:00
Lioncash
f5263cc196 thumb32: Implement exclusive loads 
Implements the remaining loads for ARMv7
 2021-04-19 19:46:19 +01:00
MerryMage
9c6332fcbd thumb32_load_store_dual: imm8 in STREX should be shifted left by 2 2021-04-19 18:57:28 +01:00
MerryMage
b2a4da5e65 block_of_code: Correct SpaceRemaining 2021-04-11 15:37:25 +01:00
Lioncash
6241ff6be2 thumb32: Implement STREX variants 
Implements the exclusive store instructions. Now all that remains for
ARMv7 load/stores to be done is the exclusive loads.
 2021-04-10 17:15:19 +01:00
MerryMage
d8066b091b decoder/arm: Complete instruction version information 2021-04-10 17:11:24 +01:00
merry
71491c0a4a
Merge pull request #596 from degasus/fix_perf_register 
backend/x64: Fix PerfMapRegister usages.
 2021-04-05 21:43:10 +01:00
MerryMage
9ab83180db {a32,a64}_interface: Clear exclusive state during an exceptional exit 
This is normally done by the ERET instruction during a service call.
 2021-04-02 19:33:28 +01:00
MerryMage
c788bcdf17 block_of_code: Enable configuration of code cache sizes 2021-04-02 11:17:46 +01:00
Markus Wick
b2acdec8cb backend/x64: Fix PerfMapRegister usages. 
Both the far code and fast_dispatch_table_lookup were missing.
 2021-04-02 00:17:07 +02:00
merry
d0372aebaf
Merge pull request #592 from lioncash/dual 
thumb32: Implement LDRD/STRD/TBB/TBH
 2021-04-01 20:54:10 +01:00
bunnei
1819c2183f
backend: x64: block_of_code: Double the total code size. (#595) 
- The current limits are being hit in yuzu with some games (e.g. newer updates of BotW and SSBU).
- Increasing this fixes slow-downs in these games due to code being recompiled.
 2021-04-01 20:53:49 +01:00
MerryMage
c4cff773b9 emit_x64_vector_floating_point: Avoid checking inputs for NaNs for three-ops where able 2021-03-28 21:54:36 +01:00
Wunk
e06933f123
block_of_code: Allow Fast BMI2 paths on Zen 3 (#593) 
BMI2 instructions such as `pdep` and `pext` have been
known to be incredibly slow on AMD. But on Zen3
and newer, the performance of these instructions
are now much greater, but previous versions of AMD
architectures should still avoid BMI2.

On Zen 2, pdep/pext were 300 cycles. Now on Zen 3 it is 3 cycles.
This is a big enough improvement to allow BMI2 code to
be dispatched if available. The Zen 3 architecture is checked for
by detecting the family of the processor.
 2021-03-27 21:36:51 +00:00
Merry
c28f13af97 emit_x64_vector: Bugfix for EmitVectorReverseBits on AVX-512: Do not reverse bytes without vector 2021-03-27 21:32:43 +00:00
Merry
4d33feb1fa emit_x64_vector: Bugfix for EmitVectorLogicalShiftRight8: shift_amount can be >= 8 2021-03-27 21:32:07 +00:00
Merry
91337788ee emit_x64_vector: Bugfix for EmitVectorLogicalShiftLeft8: shift_amount can be >= 8 2021-03-27 21:31:51 +00:00
Merry
dc37fe6e28 emit_x64_vector: Bugfix for ArithmeticShiftRightByte: shift_amount can be >= 8 2021-03-27 21:31:22 +00:00
Lioncash
5873e6b955 thumb32: Implement LDRD (immediate) 2021-03-13 15:29:56 -05:00
Lioncash
9757e2353f thumb32: Implement LDRD (literal) 2021-03-13 15:29:56 -05:00
Lioncash
a74843ca17 thumb32: Implement STRD 2021-03-13 15:29:56 -05:00
Lioncash
258ca93c53 thumb32: Implement TBB/TBH 2021-03-13 15:29:49 -05:00
Lioncash
1d0b705996 thumb32: Implement PUSH 
This can be handled as an alias for STMDB.
 2021-03-12 19:54:35 -05:00
Lioncash
9cb4790428 thumb32: Implement POP 
This can just be treated as an alias to LDMIA
 2021-03-12 19:43:47 -05:00
Lioncash
39edee70ff thumb32: Implement LDMDB/LDMEA 2021-03-12 19:35:28 -05:00
Lioncash
ae83713f4f thumb32: Simplify existing store functions into helper function 
We can also make a STM helper.
 2021-03-12 19:30:29 -05:00
Lioncash
0d887d9ecd thumb32: Implement LDMIA/LDMFD 2021-03-12 19:26:03 -05:00
Lioncash
714ccf13dd thumb32: Implement STMDB/STMFD 2021-03-12 19:05:39 -05:00
Lioncash
91c4d59da9 thumb32: Implement STMIA/STMEA 2021-03-12 19:05:15 -05:00
merry
543ba4e61f
Merge pull request #589 from lioncash/adr 
thumb32: Implement plain binary immediate ADR variants
 2021-03-12 23:10:23 +00:00
Lioncash
85b8adeb32 thumb32: Implement plain binary immediate ADR variants 
Now all the plain binary immediate instructions are implemented.
 2021-03-12 18:05:41 -05:00
Lioncash
bd02d9e27f thumb32: Implement STR immediate variants 2021-03-12 14:03:40 -05:00
Lioncash
2521314384 thumb32: Implement STRH immediate variants 2021-03-12 13:55:39 -05:00
Lioncash
cbf9027278 thumb32: Implement STRB immediate variants 2021-03-12 13:33:11 -05:00
merry
2093d2b775
Merge pull request #587 from lioncash/8dot7 
a64: Add v8.7 instruction additions to the decoder
 2021-03-10 21:19:03 +00:00
Lioncash
035580abd2 a64: Add v8.7 instruction additions to the decoder 
Adds the instructions introduced in FEAT_WFxT and FEAT_LS64/FEAT_LS64_V
in ARMv8.7
 2021-03-09 18:41:20 -05:00
Lioncash
fb30922cd1 thumb32: Add supporting decoder entry for PLD (literal) 
LDRH (literal)'s pseduocode indicates that cases where Rt specifies the
PC, that the instruction should be execured as if it were a PLD
instruction.

Curiously, however, within the ARM reference manual, the encodings in the case
that happens doesn't match up.

The bit pattern for LDRH (literal) has bit 21 set to 1, but the encoding
of PLD (literal) has bit 21 set to zero for it's only thumb encoding.
 2021-03-09 18:16:08 -05:00
Lioncash
921998f6e9 thumb32: Implement LDRSH variants 2021-03-09 18:11:33 -05:00
Lioncash
7a9bdc8f21 thumb32: Implement LDRH variants 2021-03-09 17:12:46 -05:00