MerryMage
e01583abba
A64/system: Reorder fields of SystemRegisterEncoding
...
Matches manual, which allows for easier verification of correctness.
2021-02-01 20:01:39 +00:00
MerryMage
f2345c1590
A64/system: Implement MSR/MRS for NZCV
2021-02-01 19:52:49 +00:00
Fernando Sahmkow
41521ed856
User Config: Add option to specify wall clock CNTPCT.
2020-05-03 01:40:37 +01:00
MerryMage
a8a712c801
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
MerryMage
717bd2fbb2
A64: Add hook_hint_instructions option
2020-04-22 21:04:23 +01:00
MerryMage
f96c43d422
A32: Implement FastDispatchHint
2020-04-22 20:53:46 +01:00
Lioncash
f3f60cd179
A64: Implement ISB
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Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
2020-04-22 20:53:45 +01:00
MerryMage
d1d6f4feb5
system: Implement MRS CNTFRQ_EL0
2020-04-22 20:53:45 +01:00
MerryMage
55eaa16615
a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT
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Discovered by @Subv.
Fixes incomplete fix begun in 5a91c94dca47c9702dee20fbd5ae1f4c07eef9df.
That fix fails to take into account that LinkBlock doesn't update ticks until there
are no remaining ticks to be executed.
Test added to confirm fix.
2020-04-22 20:46:21 +01:00
MerryMage
699c5f36d5
system: Simplify static_cast
2020-04-22 20:46:21 +01:00
MerryMage
3f602129f4
system: Ensure value of CNTPCT_EL0 is accurate
...
Since we currently only update the host's tick count at the end of a
block, we force an end-of-block before executing a MRS %, CNTPCT_ELO
instruction.
2020-04-22 20:46:21 +01:00
Lioncash
73b9e4b276
A64: system: Use an enum class for MRS/MSR register encodings
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Reduces the need to manually write out the register bit encodings repeatedly.
2020-04-22 20:46:15 +01:00
MerryMage
fd075d8d68
system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
2020-04-22 20:46:15 +01:00
MerryMage
c832cec96d
Correct FPSR and FPCR
2020-04-22 20:46:15 +01:00
MerryMage
e4697b1676
A64: Implement system register TPIDR_EL0
2020-04-22 20:46:15 +01:00
MerryMage
e3da92024e
A64: Implement system registers FPCR and FPSR
2020-04-22 20:46:15 +01:00
MerryMage
9e4e4e9c1d
A64: Implement system register CNTPCT_EL0
2020-04-22 20:46:15 +01:00
MerryMage
1e15283d00
A64: Implement system register CTR_EL0
2020-04-22 20:46:15 +01:00
MerryMage
2a6619d59c
A64: Implement CLREX
2020-04-22 20:46:14 +01:00
MerryMage
8756487554
A64: Partially implement MRS
2020-04-22 20:46:14 +01:00
MerryMage
bfd65bedfe
A64: Implement DSB, DMB
2020-04-22 20:46:14 +01:00
Lioncash
67443efb62
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
Lioncash
ae5dbcbed6
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
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Truly the most difficult A64 instructions to implement.
2020-04-22 20:42:46 +01:00
