7 Commits

Author	SHA1	Message	Date
Lioncash	ed6ca58058	A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero ... Fairly self-explanatory, we can leverage the existing IR functions for the purpose of these instructions. In the integer case, we can just insert function pointers into an array and index it, given all comparison primitives exist already for the integer side of things.	2020-06-20 00:50:40 +01:00
MerryMage	7402d38675	test_arm_instructions: Add vclt.f32 (zero) test	2020-06-18 17:59:44 +01:00
MerryMage	e953f67201	emit_x64_packed: PackedAbsDiffSumS8: Fix case when bits above the lower 32 bits are not zero	2020-06-12 15:24:09 +01:00
MerryMage	94d0d33e02	Fix single stepping for certain instructions ... Several issues: 1. Several terminal instructions did not stop at the end of a single-step block 2. x64 backend for the A32 frontend sometimes polluted upper_location_descriptor with the single-stepping flag We also introduce the enable_optimizations parameter to the A32 frontend.	2020-04-24 11:44:38 +01:00
MerryMage	a8a712c801	Relicense to 0BSD	2020-04-23 15:45:57 +01:00
MerryMage	cb971d3280	test_arm_instruction: Revive some old tests	2020-04-22 21:04:23 +01:00
MerryMage	39bd2c034d	constant_propagation_pass: Handle GetCarryFromOp for MostSignificantWord	2020-04-22 21:04:23 +01:00