Commit Graph

2404 Commits

Author SHA1 Message Date
MerryMage
c6ecc835b6 ASIMD: Implement VCVT (between half-precision and single-precision) 2021-05-16 23:48:29 +01:00
MerryMage
9de58f2875 assert: Check for unreachable code if DYNARMIC_IGNORE_ASSERTS isn't enabled 2021-05-16 21:46:44 +01:00
MerryMage
5bf74b5f04 reg_alloc: Determine size of spill slot with sizeof 2021-05-16 21:46:10 +01:00
MerryMage
b6bff56523 translate_thumb: Update current_instruction_size in TranslateSingleThumbInstruction 2021-05-16 10:31:30 +01:00
Wunkolo
2c0be5e18c emit_x64_vector: AVX512 Implementation of EmitVectorNarrow{32,64}
Includes a new test case with the XTN instruction to verify
the implementation
2021-05-16 10:02:49 +01:00
MerryMage
1643e8f3c6 translate_thumb: VFP/ASIMD conflict with coprocessor instructions 2021-05-15 20:54:35 +01:00
Wunkolo
105b464bc1 backend/x64: Implement HostFeature 2021-05-14 21:20:21 +01:00
MerryMage
b93ae62acf thumb32: Add coprocessor instructions 2021-05-13 18:15:35 +01:00
MerryMage
5ebe11c329 reg_alloc: Inform RegAlloc about rsp changes 2021-05-07 12:47:55 +01:00
MerryMage
05a6b5f623 translate_thumb: Permit ASIMD element or structure load/store instructions to be translated 2021-05-07 12:47:55 +01:00
sunho
cb79bfa1dc thumb32: Support setflags in shift reg instructions 2021-05-05 11:47:49 +01:00
MerryMage
075fdeaee0 thumb32: Add Rn argument to ADD/SUB (Plain Binary Immediate) 2021-05-05 11:47:49 +01:00
MerryMage
ebe44dab7a stack_layout: Ignore warning C4324 for StackLayout
We expect the structure to be padded
2021-05-04 16:26:28 +01:00
MerryMage
462c884685 frontend/A32: Correct more IT state 2021-05-04 16:25:24 +01:00
MerryMage
c5f5c1d40f frontend: Standardize emitted IR for exception raising 2021-05-04 16:14:26 +01:00
MerryMage
3b2c6afdc2 backend/x64: Move cycles_remaining and cycles_to_run from JitState to stack 2021-05-04 14:40:13 +01:00
MerryMage
d6592c7142 Remove ExceptionalExit hack 2021-05-04 14:40:13 +01:00
MerryMage
030ff82ba8 backend/x64: Move check_bit from JitState to stack 2021-05-04 14:40:13 +01:00
MerryMage
a1950d1d2f backend/x64: Move save_host_MXCSR from JitState to stack 2021-05-04 14:19:05 +01:00
MerryMage
ddbc50cee0 backend/x64: Move spill from JitState onto the stack 2021-05-04 14:18:44 +01:00
MerryMage
f8d8ea0deb thumb32: Implement MRS (register) 2021-05-04 12:43:51 +01:00
MerryMage
61333917a4 thumb32: Implement MRS (register) 2021-05-04 12:43:38 +01:00
MerryMage
a5a210a9a5 T32: Add ASIMD instructions 2021-05-04 00:09:55 +01:00
MerryMage
d1e62b9993 T32: Add VFP instructions 2021-05-04 00:09:55 +01:00
MerryMage
cd837c5b37 A32: Merge ArmTranslateVistor and ThumbTranslateVisitor 2021-05-04 00:09:55 +01:00
MerryMage
6d292e3eac decoder: Ensure more compiler-time computation
Replace with consteval when C++20 hits
2021-05-03 13:09:51 +01:00
MerryMage
795b9bea9a Remove ChangeProcessorID hack
* No library users require this hack any longer.
2021-05-01 20:33:14 +01:00
MerryMage
6759942b56 emit_x64_data_processing: Correct bug in ArithmeticShiftRight64
This branch of this implementation is unused, and thus has not been tested.
2021-04-27 18:51:23 +01:00
MerryMage
68088c277c emit_x64_data_processing: Reduce codesize of RotateRight32 for carry case 2021-04-26 21:57:22 +01:00
MerryMage
f77b98de36 emit_x64_data_processing: Reduce codesize of ArithmeticShiftRight32 for carry case 2021-04-26 21:57:08 +01:00
MerryMage
a2a687f208 emit_x64_data_processing: Reduce codesize of LogicalShiftRight32 for carry case 2021-04-26 21:56:42 +01:00
MerryMage
58ff457339 emit_x64_data_processing: Reduce codesize of LogicalShiftLeft32 for carry case 2021-04-26 21:35:06 +01:00
MerryMage
510862e50c backend/x64: Change V flag testing to cmp instead of add
Prefer a non-destructive read to a destructive read.
2021-04-26 00:26:28 +01:00
MerryMage
3f74a839b9 emit_x64_floating_point: Optimize 64-bit EmitFPRSqrtEstimate 2021-04-26 00:26:28 +01:00
MerryMage
7bc9e36ed7 emit_x64_floating_point: Optimize 32-bit EmitFPRSqrtEstimate 2021-04-26 00:26:28 +01:00
MerryMage
e19f898aa2 ir: Reorganize to new top level folder 2021-04-21 22:22:07 +01:00
MerryMage
5bec200c36 block_of_code: Add santiy check that far_code_offset < total_code_size 2021-04-21 18:26:26 +01:00
MerryMage
08ed8b4a11 abi: Consolodate ABI information into one place 2021-04-21 18:25:04 +01:00
Lioncash
f5263cc196 thumb32: Implement exclusive loads
Implements the remaining loads for ARMv7
2021-04-19 19:46:19 +01:00
MerryMage
9c6332fcbd thumb32_load_store_dual: imm8 in STREX should be shifted left by 2 2021-04-19 18:57:28 +01:00
MerryMage
b2a4da5e65 block_of_code: Correct SpaceRemaining 2021-04-11 15:37:25 +01:00
Lioncash
6241ff6be2 thumb32: Implement STREX variants
Implements the exclusive store instructions. Now all that remains for
ARMv7 load/stores to be done is the exclusive loads.
2021-04-10 17:15:19 +01:00
MerryMage
d8066b091b decoder/arm: Complete instruction version information 2021-04-10 17:11:24 +01:00
merry
71491c0a4a
Merge pull request #596 from degasus/fix_perf_register
backend/x64: Fix PerfMapRegister usages.
2021-04-05 21:43:10 +01:00
MerryMage
9ab83180db {a32,a64}_interface: Clear exclusive state during an exceptional exit
This is normally done by the ERET instruction during a service call.
2021-04-02 19:33:28 +01:00
MerryMage
c788bcdf17 block_of_code: Enable configuration of code cache sizes 2021-04-02 11:17:46 +01:00
Markus Wick
b2acdec8cb backend/x64: Fix PerfMapRegister usages.
Both the far code and fast_dispatch_table_lookup were missing.
2021-04-02 00:17:07 +02:00
merry
d0372aebaf
Merge pull request #592 from lioncash/dual
thumb32: Implement LDRD/STRD/TBB/TBH
2021-04-01 20:54:10 +01:00
bunnei
1819c2183f
backend: x64: block_of_code: Double the total code size. (#595)
- The current limits are being hit in yuzu with some games (e.g. newer updates of BotW and SSBU).
- Increasing this fixes slow-downs in these games due to code being recompiled.
2021-04-01 20:53:49 +01:00
MerryMage
c4cff773b9 emit_x64_vector_floating_point: Avoid checking inputs for NaNs for three-ops where able 2021-03-28 21:54:36 +01:00
Wunk
e06933f123
block_of_code: Allow Fast BMI2 paths on Zen 3 (#593)
BMI2 instructions such as `pdep` and `pext` have been
known to be incredibly slow on AMD. But on Zen3
and newer, the performance of these instructions
are now much greater, but previous versions of AMD
architectures should still avoid BMI2.

On Zen 2, pdep/pext were 300 cycles. Now on Zen 3 it is 3 cycles.
This is a big enough improvement to allow BMI2 code to
be dispatched if available. The Zen 3 architecture is checked for
by detecting the family of the processor.
2021-03-27 21:36:51 +00:00
Merry
c28f13af97 emit_x64_vector: Bugfix for EmitVectorReverseBits on AVX-512: Do not reverse bytes without vector 2021-03-27 21:32:43 +00:00
Merry
4d33feb1fa emit_x64_vector: Bugfix for EmitVectorLogicalShiftRight8: shift_amount can be >= 8 2021-03-27 21:32:07 +00:00
Merry
91337788ee emit_x64_vector: Bugfix for EmitVectorLogicalShiftLeft8: shift_amount can be >= 8 2021-03-27 21:31:51 +00:00
Merry
dc37fe6e28 emit_x64_vector: Bugfix for ArithmeticShiftRightByte: shift_amount can be >= 8 2021-03-27 21:31:22 +00:00
Lioncash
5873e6b955 thumb32: Implement LDRD (immediate) 2021-03-13 15:29:56 -05:00
Lioncash
9757e2353f thumb32: Implement LDRD (literal) 2021-03-13 15:29:56 -05:00
Lioncash
a74843ca17 thumb32: Implement STRD 2021-03-13 15:29:56 -05:00
Lioncash
258ca93c53 thumb32: Implement TBB/TBH 2021-03-13 15:29:49 -05:00
Lioncash
1d0b705996 thumb32: Implement PUSH
This can be handled as an alias for STMDB.
2021-03-12 19:54:35 -05:00
Lioncash
9cb4790428 thumb32: Implement POP
This can just be treated as an alias to LDMIA
2021-03-12 19:43:47 -05:00
Lioncash
39edee70ff thumb32: Implement LDMDB/LDMEA 2021-03-12 19:35:28 -05:00
Lioncash
ae83713f4f thumb32: Simplify existing store functions into helper function
We can also make a STM helper.
2021-03-12 19:30:29 -05:00
Lioncash
0d887d9ecd thumb32: Implement LDMIA/LDMFD 2021-03-12 19:26:03 -05:00
Lioncash
714ccf13dd thumb32: Implement STMDB/STMFD 2021-03-12 19:05:39 -05:00
Lioncash
91c4d59da9 thumb32: Implement STMIA/STMEA 2021-03-12 19:05:15 -05:00
merry
543ba4e61f
Merge pull request #589 from lioncash/adr
thumb32: Implement plain binary immediate ADR variants
2021-03-12 23:10:23 +00:00
Lioncash
85b8adeb32 thumb32: Implement plain binary immediate ADR variants
Now all the plain binary immediate instructions are implemented.
2021-03-12 18:05:41 -05:00
Lioncash
bd02d9e27f thumb32: Implement STR immediate variants 2021-03-12 14:03:40 -05:00
Lioncash
2521314384 thumb32: Implement STRH immediate variants 2021-03-12 13:55:39 -05:00
Lioncash
cbf9027278 thumb32: Implement STRB immediate variants 2021-03-12 13:33:11 -05:00
merry
2093d2b775
Merge pull request #587 from lioncash/8dot7
a64: Add v8.7 instruction additions to the decoder
2021-03-10 21:19:03 +00:00
Lioncash
035580abd2 a64: Add v8.7 instruction additions to the decoder
Adds the instructions introduced in FEAT_WFxT and FEAT_LS64/FEAT_LS64_V
in ARMv8.7
2021-03-09 18:41:20 -05:00
Lioncash
fb30922cd1 thumb32: Add supporting decoder entry for PLD (literal)
LDRH (literal)'s pseduocode indicates that cases where Rt specifies the
PC, that the instruction should be execured as if it were a PLD
instruction.

Curiously, however, within the ARM reference manual, the encodings in the case
that happens doesn't match up.

The bit pattern for LDRH (literal) has bit 21 set to 1, but the encoding
of PLD (literal) has bit 21 set to zero for it's only thumb encoding.
2021-03-09 18:16:08 -05:00
Lioncash
921998f6e9 thumb32: Implement LDRSH variants 2021-03-09 18:11:33 -05:00
Lioncash
7a9bdc8f21 thumb32: Implement LDRH variants 2021-03-09 17:12:46 -05:00
Lioncash
3d7e81e7d1 thumb32: Implement LDR variants 2021-03-09 13:12:15 -05:00
MerryMage
646fd05920 thumb32: Implement RSB (reg) 2021-03-06 19:49:44 +00:00
MerryMage
3f97cb1f9b thumb32: Implement SUB (reg) 2021-03-06 19:49:44 +00:00
MerryMage
17bdb54d30 thumb32: Implement CMP (reg) 2021-03-06 19:49:44 +00:00
MerryMage
a63271fd3b thumb32: Implement SBC (reg) 2021-03-06 19:49:44 +00:00
MerryMage
95189b78ef thumb32: Implement ADC (reg) 2021-03-06 19:49:44 +00:00
MerryMage
af33155ef8 thumb32: Implement ADD (reg) 2021-03-06 19:49:44 +00:00
MerryMage
41ac9971f4 thumb32: Implement CMN (reg) 2021-03-06 19:49:44 +00:00
MerryMage
e7ecd3a7ee thumb32: Implement PKHBT, PKHTB 2021-03-06 19:49:44 +00:00
MerryMage
d2d996e6ba thumb32: Implement EOR (reg) 2021-03-06 19:49:44 +00:00
MerryMage
158a13173c thumb32: Implement AND (reg) 2021-03-06 19:49:44 +00:00
MerryMage
c253b8fc51 thumb32: Implement TST (reg) 2021-03-06 19:49:44 +00:00
merry
ea5d8a3047
Merge pull request #584 from lioncash/loads
thumb32: Implement Thumb-2 Load Byte and Memory Hints instructions
2021-03-06 17:31:45 +00:00
MerryMage
531bb42ab5 thumb32: Implement B (T3) 2021-03-06 17:29:55 +00:00
MerryMage
86aa3f0701 thumb32: Implement B (T4) 2021-03-06 17:27:54 +00:00
Lioncash
52fdf801d0 thumb32: Implement LDRSB variants 2021-03-06 11:33:33 -05:00
Lioncash
fe892732cf thumb32: Implement LDRB variants 2021-03-06 11:06:30 -05:00
Lioncash
c66afadbc1 thumb32: Implement PLI variants 2021-03-06 09:55:29 -05:00
Lioncash
b2802aaf17 thumb32: Implement PLD variants 2021-03-06 09:36:51 -05:00
Lioncash
ee99fa69e9 thumb32: Add load source files
Places all the skeleton files in place.
2021-03-06 09:13:05 -05:00
Lioncash
47ab3a1450 CMakeLists: Add decoder .inc files
This makes them show up in IDE generators like XCode.
2021-03-05 21:00:31 -05:00
merry
f09e400858
Merge pull request #582 from lioncash/pbi
thumb32: Implement most plain binary immediate instructions
2021-03-05 23:20:58 +00:00
MerryMage
67e954a4cf thumb32_data_processing_plain_binary_immediate: Make invalid {S,U}SSAT16 decode undefined 2021-03-02 20:54:19 +00:00
MerryMage
52a9af3dca CMakeLists: Rework architecture detection
* Also only enable xybak/vixl on appropriate architectures
2021-03-02 20:41:38 +00:00
merry
3d418e9a4f
Merge pull request #583 from lioncash/str
thumb32: Implement STRB/STRH/STR (register)
2021-03-02 02:19:47 +00:00
Lioncash
2ac615b882 thumb32: Implement SSAT/USAT 2021-03-01 15:59:52 -05:00
Lioncash
5601aa554e thumb32: Implement STRB/STRH/STR (register) 2021-03-01 15:41:49 -05:00
MerryMage
170ab30b8e thumb32: Implement RSB (immediate) 2021-02-28 21:49:14 +00:00
MerryMage
8d33de2dcc thumb32: Implement SUB (immediate, T3) 2021-02-28 21:49:14 +00:00
MerryMage
8efb2a5b05 thumb32: Implement CMP (immediate) 2021-02-28 21:49:14 +00:00
MerryMage
78330e634f thumb32: Implement SBC (immediate) 2021-02-28 21:49:14 +00:00
MerryMage
e6b925146b thumb32: Implement ADC (immediate) 2021-02-28 21:49:14 +00:00
MerryMage
8f9e052c93 thumb32: Implement ADD (imm, T3) 2021-02-28 21:49:14 +00:00
MerryMage
30442ee1f4 thumb32: Implement CMN (immediate) 2021-02-28 21:49:14 +00:00
merry
421548ceef
Merge pull request #581 from lioncash/8dot6
a64: Add v8.6 instruction encoding additions
2021-02-27 21:54:08 +00:00
Lioncash
385f907463 a64: Add v8.6 instruction encoding additions
Keeps the instruction listing up to date.
2021-02-27 16:25:13 -05:00
Lioncash
9d5505422f thumb32: Implement ADD/SUB (imm 2) 2021-02-25 09:56:05 -05:00
Lioncash
68885fdb3c thumb32: Implement SBFX/UBFX 2021-02-25 09:37:15 -05:00
Lioncash
7334914047 thumb32: Implement BFC/BFI 2021-02-25 09:27:05 -05:00
Lioncash
ba7cbe7cf6 thumb32: Implement SSAT16/USAT16 2021-02-25 09:13:46 -05:00
Lioncash
725d712c88 thumb32: Simplify register shift implementations to common function 2021-02-23 04:53:50 -05:00
Lioncash
a7a9ed69b7 thumb32: Implement ROR (register) 2021-02-23 04:52:29 -05:00
Lioncash
abf3548b2a thumb32: Implement ASR (register) 2021-02-23 04:43:11 -05:00
Lioncash
e06d4bcbb2 thumb32: Implement LSR (register) 2021-02-23 04:40:43 -05:00
Lioncash
fdd379a36c thumb32: Implement LSL (register) 2021-02-23 04:40:40 -05:00
merry
ac32175eff
Merge pull request #579 from lioncash/bxj
thumb32: Implement BXJ
2021-02-22 15:01:08 +00:00
Lioncash
89838c5ce4 thumb32: Implement BXJ
We handle this as a regular BX call, given we don't support Jazelle.
2021-02-22 07:45:21 -05:00
Lioncash
de8e977bb1 thumb32: Implement SEVL 2021-02-22 07:34:42 -05:00
Lioncash
a4c9ec645f thumb32: Implement SEV 2021-02-22 07:34:42 -05:00
Lioncash
565a20b096 thumb32: Implement WFI 2021-02-22 07:34:42 -05:00
Lioncash
3dc33c1257 thumb32: Implement WFE 2021-02-22 07:34:42 -05:00
Lioncash
48fe7afe72 thumb32: Implement YIELD 2021-02-22 07:34:42 -05:00
Lioncash
a73ea9e111 thumb32: Implement NOP 2021-02-22 07:34:39 -05:00
MerryMage
29d7cbd899 thumb32: Ensure CPSR.IT state is always up to date 2021-02-22 00:27:16 +00:00
MerryMage
f5dd7122a2 EmitFPVectorMulAdd: Correct optimization flag (Unsafe_UnfuseFMA -> Unsafe_InaccurateNaN) 2021-02-21 21:30:20 +00:00
merry
75f4978da5
Merge pull request #577 from lioncash/barrier
thumb32: Implement barrier instructions and CLREX
2021-02-19 22:51:13 +00:00
Lioncash
3890590b4f thumb32: Implement CLREX 2021-02-19 00:02:57 -05:00
Lioncash
5543e4f9eb thumb32: Implement ISB 2021-02-19 00:01:24 -05:00
Lioncash
085147b5a4 thumb32: Implement DMB 2021-02-18 23:59:34 -05:00
Lioncash
368a8630e0 thumb32: Implement DSB 2021-02-18 23:58:12 -05:00
Lioncash
5602db88f4 thumb32: Implement MOVW 2021-02-18 23:52:06 -05:00
Lioncash
d05c706ff4 thumb32: Implement MOVT 2021-02-18 23:52:03 -05:00
MerryMage
f568687bd9 thumb32: Implement EOR (immediate) 2021-02-18 20:51:13 +00:00
MerryMage
8fd7ec3989 thumb32: Implement TEQ (immediate) 2021-02-18 20:49:06 +00:00
MerryMage
efbc8cef53 thumb32: Implement ORN (immediate) 2021-02-18 20:48:55 +00:00
MerryMage
08f046036c thumb32: Implement MVN (immediate) 2021-02-18 20:19:45 +00:00
MerryMage
cafa687684 thumb32: Implement ORR (immediate) 2021-02-18 01:28:03 +00:00
MerryMage
b2f0575fee thumb32: Implement MOV (immediate) 2021-02-18 01:28:03 +00:00
MerryMage
3dcc882fbf thumb32: Implement BIC (immediate) 2021-02-18 01:28:03 +00:00
MerryMage
6f3c5dc1d9 thumb32: Implement AND (immediate) 2021-02-18 01:28:03 +00:00
MerryMage
5bf676d93e thumb32: Implement TST (immediate) 2021-02-18 01:05:45 +00:00
Sunho Kim
069beb5228 A32: Add ThumbExpandImm and ThumbExpandImm_C
These are used by many thumb2 instructions
2021-02-17 23:45:51 +00:00
sunho
43a1a523f6 A32: Fix thumb32 BL and BLX
More fields required
2021-02-17 23:18:05 +00:00
MerryMage
df027a7998 thumb32: Split thumb32 file into branch and control 2021-02-17 23:18:05 +00:00