SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-06 02:26:30 +00:00
Code Issues Packages Projects Releases Wiki Activity
Files
4b3d70de5fc70a1f39072d222cc1c8835a62dd72
dynarmic/src/frontend/A64/translate/impl
History
Lioncash 4b3d70de5f simd_shift_by_immediate: Factor out common code in shift instructions 
Gets rid of partial duplication of the same code for instructions that only have a small behavior difference to them.

e.g. The only difference between SSHR and SSRA is that SSRA adds an accumulator before storing the result.
2020-04-22 20:46:16 +01:00
..
branch.cpp
Implement DC instructions
2020-04-22 20:46:14 +01:00
data_processing_addsub.cpp
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
2020-04-22 20:44:38 +01:00
data_processing_bitfield.cpp
A64: Implement EXTR
2020-04-22 20:46:12 +01:00
data_processing_conditional_compare.cpp
A64: Implement CCMP (immediate)
2020-04-22 20:46:13 +01:00
data_processing_conditional_select.cpp
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
2020-04-22 20:44:38 +01:00
data_processing_crc32.cpp
A64: Implement CRC32
2020-04-22 20:46:12 +01:00
data_processing_logical.cpp
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
2020-04-22 20:44:38 +01:00
data_processing_multiply.cpp
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
2020-04-22 20:46:13 +01:00
data_processing_pcrel.cpp
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
2020-04-22 20:44:38 +01:00
data_processing_register.cpp
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
2020-04-22 20:46:13 +01:00
data_processing_shift.cpp
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
2020-04-22 20:44:38 +01:00
exception_generating.cpp
Implement DC instructions
2020-04-22 20:46:14 +01:00
floating_point_compare.cpp
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2020-04-22 20:46:13 +01:00
floating_point_conditional_compare.cpp
A64: Implement FCCMPE
2020-04-22 20:46:13 +01:00
floating_point_conditional_select.cpp
A64: Implement FCSEL
2020-04-22 20:46:13 +01:00
floating_point_conversion_fixed_point.cpp
A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
2020-04-22 20:46:15 +01:00
floating_point_conversion_integer.cpp
A64: Implement SIMD instructions USHLL, USHLL2
2020-04-22 20:46:13 +01:00
floating_point_data_processing_one_register.cpp
A64: Implement FSQRT (scalar)
2020-04-22 20:46:14 +01:00
floating_point_data_processing_two_register.cpp
A64: Implement FMINNM (scalar)
2020-04-22 20:46:15 +01:00
impl.cpp
A64/translate: Amend I() to also handle u8 and u16 immediates
2020-04-22 20:46:15 +01:00
impl.h
A64/translate: Amend I() to also handle u8 and u16 immediates
2020-04-22 20:46:15 +01:00
load_store_exclusive.cpp
Exclusive fixups
2020-04-22 20:46:14 +01:00
load_store_load_literal.cpp
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
2020-04-22 20:44:38 +01:00
load_store_multiple_structures.cpp
load_store_multiple_structures: Improve IR codegen for selem == 1 case
2020-04-22 20:46:14 +01:00
load_store_register_immediate.cpp
A64: NOP immediate variant of PRFM
2020-04-22 20:46:15 +01:00
load_store_register_pair.cpp
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
2020-04-22 20:44:38 +01:00
load_store_register_register_offset.cpp
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
2020-04-22 20:46:14 +01:00
load_store_register_unprivileged.cpp
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
2020-04-22 20:44:38 +01:00
move_wide.cpp
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
2020-04-22 20:44:38 +01:00
simd_aes.cpp
A64: Implement AESD
2020-04-22 20:46:13 +01:00
simd_copy.cpp
A64: Implement DUP (element), scalar variant
2020-04-22 20:46:14 +01:00
simd_crypto_four_register.cpp
A64: Implement EOR3 and BCAX
2020-04-22 20:46:15 +01:00
simd_extract.cpp
A64: Implement EXT
2020-04-22 20:46:15 +01:00
simd_modified_immediate.cpp
A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated
2020-04-22 20:46:15 +01:00
simd_permute.cpp
A64: Implement ZIP2
2020-04-22 20:46:15 +01:00
simd_scalar_pairwise.cpp
A64: Implement ADDP (scalar)
2020-04-22 20:46:14 +01:00
simd_scalar_three_same.cpp
A64: Implement SUB (vector), scalar variant
2020-04-22 20:46:13 +01:00
simd_scalar_two_register_misc.cpp
A64: Implement REV64
2020-04-22 20:46:15 +01:00
simd_sha512.cpp
A64: Implement RAX1
2020-04-22 20:46:15 +01:00
simd_sha.cpp
A64: Implement SHA1H
2020-04-22 20:46:15 +01:00
simd_shift_by_immediate.cpp
simd_shift_by_immediate: Factor out common code in shift instructions
2020-04-22 20:46:16 +01:00
simd_three_different.cpp
A64: Implement USUBW/USUBW2
2020-04-22 20:46:15 +01:00
simd_three_same.cpp
A64: Implement FMUL (vector)
2020-04-22 20:46:15 +01:00
simd_two_register_misc.cpp
A64: Implement RBIT (vector)
2020-04-22 20:46:15 +01:00
sys_dc.cpp
Implement DC instructions
2020-04-22 20:46:14 +01:00
system.cpp
A64: system: Use an enum class for MRS/MSR register encodings
2020-04-22 20:46:15 +01:00