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8bbc9fdbb6fb8a4e0a8b5fa7ff350f3aab72cae0
dynarmic/src/frontend/A32/translate/impl
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MerryMage 8bbc9fdbb6 A32: Implement ASIMD VTBX
2020-06-20 22:35:31 +01:00
..
asimd_load_store_structures.cpp
frontend: Relocate ExtReg handling to types.h
2020-05-24 23:55:47 +01:00
asimd_misc.cpp
A32: Implement ASIMD VTBX
2020-06-20 22:35:31 +01:00
asimd_one_reg_modified_immediate.cpp
asimd_one_reg_modified_immediate: Use {Get,Set}Vector
2020-05-28 20:40:26 +01:00
asimd_three_same.cpp
A32: Implement ASIMD VPADD (integer)
2020-06-20 21:22:14 +01:00
asimd_two_regs_misc.cpp
A32: Implement ASIMD VPADAL (integer)
2020-06-20 22:28:47 +01:00
asimd_two_regs_scalar.cpp
A32: Implement ASIMD VMUL (scalar)
2020-06-20 20:34:08 +01:00
asimd_two_regs_shift.cpp
asimd: Prevent misdecodes from occurring
2020-06-18 15:04:48 -04:00
barrier.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
branch.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
coprocessor.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
crc32.cpp
crc32: Remove unnecessary masking
2020-06-04 20:33:46 +01:00
data_processing.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
divide.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
exception_generating.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
extension.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
hint.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
load_store.cpp
fuzz_arm: Ensure all instructions are fuzzed
2020-05-10 13:57:39 +01:00
misc.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
multiply.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
packing.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
parallel.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
reversal.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
saturated.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
status_register_access.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
synchronization.cpp
A32 global exlcusive monitor
2020-06-16 17:54:21 +01:00
thumb16.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
thumb32.cpp
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
translate_arm.h
A32: Implement ASIMD VTBX
2020-06-20 22:35:31 +01:00
translate_thumb.h
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
vfp.cpp
A32: Implement ASIMD VDUP (ARM core register)
2020-06-20 16:02:43 +01:00